Boots – shoes – and leggings
Patent
1993-02-09
1996-02-20
Chan, Eddie F.
Boots, shoes, and leggings
395455, 395463, 364DIG1, 36424341, 36424612, G06F 1212
Patent
active
054936675
ABSTRACT:
An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.
REFERENCES:
patent: 4513367 (1985-04-01), Chan et al.
patent: 5019971 (1991-05-01), Lefskey et al.
patent: 5043885 (1991-08-01), Robinson
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5283876 (1994-02-01), Tague
Huck Scott B.
Lai Konrad K.
Shenoy Sunil R.
Smith Larry O.
Chan Eddie F.
Intel Corporation
Nguyen Hiep T.
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