Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1998-10-29
2001-03-20
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06204708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital computer systems and specifically to digital computer systems which rely on master-slave latches or flip-flops. The invention provides an apparatus and method for generating quickly slewing clock signals with non-overlapping duty cycles from a master clock that has relatively slow rise and fall times.
2. Description of the Prior Art
Referring to
FIG. 1
, the current state of the art describes a master-slave latch combination in which data is clocked into the master latch
20
and slave latch
40
through a two sets of gating transistor pairs
10
and
30
, respectively, by a master clock CLK and its complement
CLK
1
. D indicates the input data and Q represents the static state output of D after proper latching by the master latch
20
and the slave latch
40
. The master clock signal CLK and its complement
CLK
are depicted in FIG.
2
.
1
The conventional method to indicate a complementary signal is to overline the signal. However, due to a word processing limitation, following this convention is not possible. Thus, in the text of this application the symbol for a complementary signal is set for as the signal underlined (e.g.
CLK
).
When properly operating, the master clock CLK goes from low to high, the gating transistor pair
10
is conducting and data is permitted to pass into the master latch
20
. Also at this time, because the clock signals are inverted at gating transistor pair
30
, this transistor pair is switched off and data is not permitted to pass into the slave latch
40
.
When the master clock CLK reverses state, i.e. from high to low, the first gating transistor pair
10
ceases to conduct. However, the second gating transistor pair
30
begins conducting and the data which was latched into the master latch
20
is now permitted to pass into the slave latch
40
. After a brief propagation delay, the data is latched and stable at output Q.
Thus, when the master-slave latch is operating properly, latching occurs in two separate, discrete steps. These two steps provides for stable data at output Q. However, a problem arises during slow rise and fall times of the master clock CLK.
The problem during the clock transition characterized by relatively slow rise and fall times is that both gating transistor pairs
10
and
30
may be partially conducting at the same time. This will result in the data racing through the master-slave latch pair
20
and
40
without achieving a steady state. This occurs when the two step process described above is circumvented because of overlapping master clock signals as a result of relatively slow rise and fall times. Therefore, a need existed to provide a master-slave latch pair with non-overlapping clock signals to permit proper latching of data in a two step process for master-slave latches.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a master-slave flip-flop which prevents data from racing through the device without being properly latched.
It is another object of the present invention to provide a master-slave flip-flop which prevents partial conduction of the gating transistor pairs.
It is another object of the present invention to provide an improved clock generator which produces non-overlapping clock signals from a master clock signal.
It is another object of the present invention to combine the non-overlapping clock signals provided by the improved clock generators with gating transistor pairs and master-slave latches to preserve the two, discrete latching steps of a master-slave flip-flop.
In accordance with one embodiment of the present invention, an improved master-slave flip-flop comprises a master gating transistor pair, a master latch coupled to the master gating transistor pair, a slave gating transistor pair coupled to the master latch, a slave latch coupled to the slave gating transistor pair, a clock generator coupled to the master gating transistor pair, a second clock generator coupled to the master gating transistor pair, a third clock generator coupled to the slave gating transistor pair, and a fourth clock generator coupled to the slave gating transistor pair.
In accordance with another embodiment of the present invention, a clock generator is comprised of a current limiter and an inverter coupled to the current limiter. Furthermore, the current limiter may be implemented as a current mirror.
In accordance with another embodiment of the present invention the trip point of the inverter is adjusted by means of the current limiter or by geometrical manipulation of the CMOS devices which comprise the inverter.
In accordance with another embodiment of the present invention, non-overlapping clocks may be derived from a single master clock signal by the clock generators.
In accordance with another embodiment of the present invention, non-overlapping clocks may be derived from a single master clock signal and the complement of the master clock signal.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 4761568 (1988-08-01), Strongski
patent: 4806804 (1989-02-01), O'Leary
patent: 5081380 (1992-01-01), Chen
patent: 5446417 (1995-08-01), Korhonen et al.
patent: 5675279 (1997-10-01), Fujimoto et al.
patent: 5705944 (1998-01-01), Mou et al.
patent: 5719878 (1998-02-01), Yu et al.
patent: 5751176 (1998-05-01), Sohn et al.
patent: 5929680 (1999-07-01), Lim
Baker & Botts L.L.P.
Microchip Technology Incorporated
Tran Toan
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