Apparatus and method for an improved content addressable memory

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364DIG1, 364DIG2, 364253, 364243, 395435, 365 49, G06F 1206, G11C 1500

Patent

active

054407095

ABSTRACT:
A content addressable memory, utilizing address recognition mechanism, comprising a Random Access Memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entity as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment, the RAM comprises an array of n RAMs, wherein the at least a portion of a data entity is segmented into n slices. Each of the slices is used as an address to a respective one of said array of n RAMs.

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T. Ogura et al., "Content Addressable Memory LSI Technology and the Future", Japanese Electronic Communications Institute, vol. 69, No. 7, Jul. 1986, pp. 745-751.

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