Apparatus and method for an extended arithmetic logic unit for e

Details Apparatus and method for an extended arithmetic logic unit for e Apparatus and method for an extended arithmetic logic unit for e

1987-05-15

1989-03-07

Harkcom, Gary V.

Boots, shoes, and leggings

364748, 364768, G06F 750

Patent

active

048112720

ABSTRACT:
Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.

REFERENCES:
patent: 3814925 (1974-06-01), Spannagel
patent: 4366548 (1982-12-01), Kregness et al.
patent: 4573137 (1986-02-01), Ohhashi
patent: 4682303 (1987-07-01), Uya
Earle et al., "Exponent Differences and Preshifter", IBM Tech. Disclosure Bulletin, vol. 9, No. 7, Dec. 1966, pp. 848-849.
Mead et al., "Introduction to VLSI Systems", Addison-Wesley Publishing Comp., 1980, pp. 150-154.

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