Patent
1996-01-02
1998-10-13
Coleman, Eric
395389, G06F 930
Patent
active
058225595
ABSTRACT:
A microprocessor is provided, including a plurality of early decode units configured to detect double dispatch instructions and to dispatch these instructions to a pair of decode units. More complex instructions are executed by an MROM unit in a serialized fashion. Simpler instructions are dispatched to a single decode unit. The early decode units partially decode the instructions (including encoding the instruction prefix into a single prefix byte), and the decoding is completed by a plurality of decode units. The present microprocessor additionally detects the more complex instructions prior to instruction decode and dispatches the instructions to an MROM unit.
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Narayan Rammohan
Tran Thang M.
Advanced Micro Devices , Inc.
Coleman Eric
Kivlin B. Noel
Merkel Lawrence J.
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