Apparatus and method for adaptively adjusting a timing loop

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Details

C375S326000, C375S376000, C375S372000, C375S344000, C327S156000

Reexamination Certificate

active

06993104

ABSTRACT:
A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time. By adaptively adjusting the parameters of the timing loop based upon frequency errors, the present invention decreases the amount of time required for a receiver to train its timing loop to, and acquire timing from, a received data signal without introducing jitter into the signal.

REFERENCES:
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patent: 6018556 (2000-01-01), Janesch et al.
patent: 6081563 (2000-06-01), Taga et al.
patent: 6337589 (2002-01-01), Ooishi
patent: 6525578 (2003-02-01), Ooishi
patent: 6850577 (2005-02-01), Li
patent: 2004/0047875 (2004-03-01), Itani et al.

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