Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2000-09-27
2004-09-07
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S035000
Reexamination Certificate
active
06789183
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the data processing apparatus and, more particularly, to the specialized high performance processors generally referred to as digital signal processing units. This invention relates specifically to the reduction of energy in digital signal processing units that have a plurality of digital signal processors, the digital signal processors having the further property that signal groups can directly exchanged therebetween.
2. Background of the Invention
As the need for increasing computation power has been recognized, part of the response to this need has been the incorporation of more than one digital signal processors in a digital signal processing unit. Referring to
FIG. 1
, a digital signal processing unit
1
having two digital signal processors, according to the prior art, is shown. A first digital signal processor
10
includes a core processing unit
12
(frequently referred to as a processing core), a direct memory access unit
14
, a memory unit or memory units
16
, and a serial port or serial ports
18
. The memory unit
16
stores the signal groups that are to be processed or that assist in the processing of the signal groups to be processed by the core processing unit
12
. The core processing unit
12
performs the bulk of the processing of signal groups in the memory unit. The direct memory access unit
14
is coupled to the core processing unit
12
and to memory unit
16
and mediates the signal group exchange therebetween. The serial port
18
exchanges signal groups with components external to the digital signal processing unit
1
. The core processing unit
12
is coupled to the serial port
18
and to the memory unit
16
and controls the exchange of signal groups between these components.
FIG. 1
also includes a second digital signal processor
10
′. The second digital signal processor
10
′ is a replica of the first digital signal processor
10
and includes a core processing unit
12
′, a direct memory access unit
14
′, a memory unit
16
′, and a serial port
18
′. The functionality and inter-relationships of the components of the digital signal processors
10
and
10
′ is the same.
The digital signal processor is typically designed and implemented to have limited functionality, but functions that must be repeated and performed rapidly. The fast fourier transform (FFT) calculation and the Viterbi algorithm decoding are two examples where digital signal processors have been utilized with great advantage. To insure that the digital signal processors operate with high efficiency, the core processing is generally optimized for the performance of the limited functionality. Part of the optimization process involves the off-loading, to the extent possible, any processing not directed toward the optimized function. Similarly, the exchange of signal groups involving the core processing unit and the memory unit has been assigned to the direct memory access controller.
In addition, many of the applications for which the digital signal processing units are the best candidates are also applications in which low power consumption is of high importance, e.g. cell phones, pagers, etc. However, for a variety of reasons such as the increased computational load, the inclusion of plurality of digital signal processors in a single digital signal processing unit has become increasingly important. As will be clear, the inclusion of a plurality of digital signal processors in a single digital signal processing unit has the effect of increasing the power consumption of the unit.
In the past, portions of the digital signal processor could be placed in an IDLE mode. In this mode of operation, the clock signal is removed from all or part of the digital signal processor. Because in the absence of a clock signal, the apparatus remains in a low energy mode until the clock signal is reapplied.
Referring to
FIG. 2A
, the block diagram of a digital signal processors
10
,
10
′ capable of implementing an IDLE mode of operation, according to the prior art, is shown. The core processing unit
12
,
12
′, the direct memory access controller
14
,
14
′, the memory unit
16
,
16
′ and the serial port
18
,
18
′, have the same relationship in the digital signal processor
10
,
10
′ as in FIG.
1
. In addition, an external clock signal is applied to a clock buffer unit
21
,
21
′. The clock buffer unit can include a phase-locked loop (not shown). A clock signal from the clock buffer unit
21
,
21
′ is applied to the core processing unit
12
,
12
′. In particular, the clock signal is applied to a clock control unit
121
,
121
′ of the core processing unit
12
,
12
′. From the clock control units
121
,
121
′, a clock signal is transmitted to the direct memory access controller
14
,
14
′ and to the serial port.
18
,
18
′. From the direct memory access controller
14
,
14
′, the clock signals are distributed to the memory unit
16
,
16
′. (Note the distribution of clock signals described here is meant to be illustrative. Other systems of the distribution of clock signals will be clear to those familiar with digital signal processors.) As will be clear to those skilled in the art, the presence of clock signals is necessary for the operation of the digital signal processor and each of components thereof. In the absence of clock signal, the apparatus of the digital signal processor remains in IDLE state, a state of the processing apparatus that consumes a reduced amount of power in the absence of clock signals. It is desirable feature of digital signal processing units for certain application that the processing apparatus be in the IDLE mode when ever the signal groups are not being manipulated.
Referring next to
FIG. 2B
, the operation of the clock controller unit
121
of the core processing unit
12
is illustrated. The clock signal from the clock buffer unit
21
is applied to a first input terminal of logic AND gate
124
and to a first input terminal of logic AND gate
125
. A second input terminal of logic AND gate
124
is coupled to an output terminal of latch unit
122
, while the second input of logic AND gate
125
is coupled to an output terminal of latch unit
123
. The latch units
122
and
123
receive external control signals on first input terminals. The external control signals set and maintain a positive logic signal at the output of the latch units
122
and
123
. An IDLE signal
0
and IDLE signal
1
are applied to the second input terminals of latch unit
122
and latch unit
123
, respectively. The IDLE signal
0
and the IDLE signal
1
remove the positive latch signal from the output terminals of the latch units to which they are applied. The operation of the clock control unit
121
can be understood as follows. When the latch units
122
and
123
are set, a positive logic signal is applied to an input terminal of logic AND gate
124
and the input terminal of logic AND gate
125
respectively. The presence of a positive logic signal on one input terminal of logic AND gate
124
and one input terminal of logic AND gate
125
results in the clock signal being applied to the output terminal of logic AND gates
124
and
125
, respectively. The logic AND gate
124
applies a clock signal to the core processing unit
12
while the logic AND gate
125
applies a clock signal to the remainder of the digital signal processor. The positive signals at the output of the latch units
122
and
123
are the result of an application of control signals to the set input terminal of the latch units. The external control signal indicates that need for the processing activity (and hence the application of the clock signal) by at least portion of the digital signal processor
10
. For example, when signal groups are applied to the serial port
18
of the digital signal processor, the serial port
18
and the core processing unit
12
be activate
Jones Jason A.
McGonagle Kevin A.
Smith Patrick J.
Brady W. James
Holloway William W.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai Henry W. H.
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