Patent
1994-12-06
1997-06-10
Swann, Tod R.
395412, 395466, 395474, G06F 1314, G06F 1200
Patent
active
056385323
ABSTRACT:
Computer systems using a processor that is capable of operating in a system management mode (SMM) employ a dedicated system management RAM (SMRAM). The processor uses the SMRAM when the processor is performing a task associated with the SMM. The processor is capable of generating a range of system addresses. The range includes a particular subrange of system addresses that are used for accessing the SMRAM. A memory controller decodes the system addresses generated by the processor and enables access to the SMRAM, regardless of whether the processor is operating in the SMM, when the controller decodes a system address of the particular subrange. The range of system addresses also includes a second subrange. The memory controller also enables access to the SMRAM when the processor is operating in the SMM and the controller decodes a system address of the second subrange. The memory controller indicates to the processor whether data associated with the enabled SMRAM can be stored in a cache memory.
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Foster Mark J.
Frame Robert C.
Digital Equipment Corporation
Fisher Arthur W.
Hudgens Ronald C.
King , Jr. Conley B.
Steubing Mary M.
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