Multiplex communications – Channel assignment techniques – Details of circuit or interface for connecting user to the...
Reexamination Certificate
1995-11-09
2001-04-03
Chin, Wellington (Department: 2664)
Multiplex communications
Channel assignment techniques
Details of circuit or interface for connecting user to the...
C370S503000
Reexamination Certificate
active
06212197
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
This invention is directed to a method and apparatus for a cross-connected Time Division Multiplexed (TDM) digital audio bus for computer systems or stand alone recording/mixing systems. More specifically, the invention is directed toward the connection of multiple nodes to form a data network for processing and recording data in a digital audio system.
2. Discussion of the Related Art
Central conference controllers and Time Division Multiplex Networks are presently used in telephone systems. In these networks, remote stations consisting of telephones and data processing apparatus are connected to a central processing system. The processor at the central processing system receives data from each station, processes the data, and redistributes the processed data to all stations on the network. Examples of conference controllers using a central processing station are disclosed in U.S. Pat. Nos: 4,271,502, 4,224,688 and 5,027,347.
U.S. Pat. No. 4,646,288, entitled “Multiline Accumulator/Multiplexer”, issued to Shumway discloses a multiplexer that can be used as a central processing control station for conferencing. In the system disclosed by Shumway, the data received from Time Division Multiplexed channels is summed in an accumulator. Shumway discloses a buffer that is alternatively connected to a TDM bus and to the accumulator to receive data from the TDM bus and provide the data to the accumulator. The data summed in the accumulator is then distributed. The accumulator/multiplexer is a simplex system that provides for limited one way communication between a client and the TDM bus.
U.S. Pat. No. 4,575,845, entitled “Time Division Multiplex Conferencer”, issued to L. Baranyai et al, discloses a simplex (one-way) digital audio mixing system. The system disclosed by Baranyai performs similarly to that of Shumway described above, except that Baranyai does not disclose storage (i.e. a buffer) of the digital audio data received from the TDM bus prior to providing the data to the accumulator. This lack of storage allows only one opportunity per TDM time frame to acquire data and sum it with other incoming data. Since the data flow in Baranyai is simplex, a second controller is required for full duplex communication.
The prior art systems include several limitations that restrict their use in a digital audio system. In conferencing systems of the prior art, all signals received over the TDM bus have the same gain and are summed before the data is presented to the client. These conference networks of the prior art are limited in that a large number of channels slows the response time of the network. Since there is not buffering, or buffering only prior to the accumulator, the data order is fixed to the same order as the time slots across the bus, and the client has essentially no control over the order in which it will see the data.
The prior art is also limited in that a master clock of the TDM bus is synchronous with a division of time slots on the bus and the sample rate of the data. In these systems, the data transfer rate, the length of each time slot, and the sample rate are directly tied to the master clock rate. These systems do not have flexibility in terms of the number of time slots provided versus sample rate. Once the sample rate is chosen in these systems, the master clock is fixed, or if the master clock is chosen, the sample rate is fixed.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a network interface module is provided for a time division multiplexed network that transfers data among clients of the network. The network has a system clock signal with a clock rate and period that defines bus cycles of the network. Each of the bus cycles of the network has a number of time slots for transmitting data over the network, each of the time slots corresponding to one channel of the network. The network interface module comprises first and second clock circuits. The first clock circuit generates a first clock signal having a clock rate that is greater than the number of time slots multiplied by the system clock rate, and having a period that defines a duration of each time slot. The first clock signal is asynchronous with the system clock signal. The second clock circuit receives the first clock signal and the system clock signal and generates a start signal indicating a start of a bus cycle.
According to another aspect of the present invention a method is provided for providing timing control for the transfer of data over a time division multiplexed network. The method includes steps of detecting a start of a bus cycle of the network and generating a second clock signal having a period corresponding to a duration of a time slot of the network. The period of the second clock signal, multiplied by the number of time slots of a bus cycle of the network, is less than a duration of the bus cycle.
According to another aspect of the present invention, a network interface module for a time division multiplexed network is provided. The network interface module comprises a client interface circuit, a network interface circuit, a memory, and an indirection table. The indirection table stores relationships between channels of the network and corresponding memory locations within the memory, and provides the relationships to the memory so that data corresponding to a particular channel of the network is stored in a specified memory location.
According to yet another aspect of the present invention, a method for storing and retrieving data in a memory of a time division multiplexed network is provided. The method includes steps of assigning a number of time slots of a bus cycle of the network as either inbound or outbound channels of a client coupled to the memory, and assigning a memory location within the memory for each of the inbound and outbound channels of the client.
According to another aspect of the present invention a network interface module for a time division multiplexed network is provided. The network interface module comprises a memory having a plurality of memory locations for storing data samples of the network, a client interface circuit that provides an interface between a client of the network and the memory, a first register for storing data samples, and a second register for storing data samples. The memory, in a first mode of operation of the network interface module, receives from the client, prior to the start of a bus cycle of the network, first and second addresses respectively corresponding to first and second memory locations of first and second data samples to be read from the memory in the bus cycle. The memory provides the first and second data samples to the first and second registers respectively, so that the data samples can be accessed during the bus cycle without memory access time delays.
In another aspect of the present invention, a method is provided for reading data from a memory of a time division multiplexed network. The method comprises steps of receiving, prior to the start of a bus cycle of the network, first and second addresses corresponding to first and second memory locations of first and second data samples to be read from the memory in the bus cycle, reading the first and second data samples from the memory, storing the data samples in temporary storage locations, and transferring the data samples to a client of the network during the bus cycle.
REFERENCES:
patent: 4224688 (1980-09-01), Ciancibello et al.
patent: 4271502 (1981-06-01), Goutmann et al.
patent: 4575845 (1986-03-01), Baranyai et al.
patent: 4646288 (1987-02-01), Shumway
patent: 4797877 (1989-01-01), Pope et al.
patent: 4819228 (1989-04-01), Baran et al.
patent: 5027347 (1991-06-01), Malkki
patent: 5165023 (1992-11-01), Gifford
patent: 5197065 (1993-03-01), Calvignac et al.
patent: 5235594 (1993-08-01), Lee
patent: 5255264 (1993-10-01), Cotton et al.
patent: 5280482 (1994-01-01), Kitamura et al.
patent: 5317693 (1994-05-01), Cuenod et al.
patent: 5357511 (1994-10-01), DiNapoli et al.
patent: 5381413
Christensen Steven G.
Clementson David D.
Jasmin James L.
Avid Technology Inc.
Chin Wellington
Fish & Neave
Ingerman Jeffrey H.
Yao Kwang B.
LandOfFree
Apparatus and method for accessing memory in a TDM network does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for accessing memory in a TDM network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for accessing memory in a TDM network will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2507672