Apparatus and method for accessing a plurality of computer devic

Details Apparatus and method for accessing a plurality of computer devic Apparatus and method for accessing a plurality of computer devic

1993-12-30

1995-05-09

Lall, Parshotam S.

395162, 395275, 395375, G06F 1310

Patent

active

054148316

ABSTRACT:
An apparatus and method for accessing a plurality of computer devices having common memory or input-output addresses on buses operating at different speeds. The present invention detects a CPU address request and issues a local bus acknowledge thereto which prevents the CPU core logic from processing the instruction on the other buses. The present invention processes the instruction and upon completion thereof, asserts both CPU BOFF and READY signals on the computer system local bus. The CPU receives the BOFF signal, releases control of the local bus and ignores the READY signal. When the present invention releases the asserted BOFF signal, it then ignores the next local bus cycle because this next local bus signal will be the same as the previous bus cycle. The next CPU bus cycle contains the same information as the previous cycle, and the computer system core logic issues appropriate commands to the other bus interface such as an ISA bus. The present invention monitors the CPU READY signal and, once detected, the present invention re-enables its local bus decode logic in anticipation of the next CPU bus cycle.

REFERENCES:
patent: 4713759 (1987-12-01), Yamagishi et al.
patent: 4839794 (1989-06-01), Okura
patent: 4912698 (1990-03-01), Bitzinger et al.
patent: 5045995 (1991-09-01), Levinthal et al.
patent: 5065343 (1991-10-01), Inoue
patent: 5230041 (1993-07-01), Dinwiddie, Jr. et al.

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