Apparatus and method for accelerating floating point addition an

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G06F 738

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048520390

ABSTRACT:
The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. The effective subtraction operation can be accelerated by using two methods of execution depending on whether the absolute value of the difference between the arguments of the exponents, ABS{DELTA(E)} is .ltoreq.1 or >1. The procedure for ABS{DELTA(E)}.ltoreq.1 requires more major process steps than the situation where ABS{DELTA(E)}.ltoreq.1. To accelerate only the procedure having more major process steps, the two least significant bits of both exponent arguments are examined and based on the examination, the lengthier procedure can be initiated in parallel with the process step determining the value of ABS{DELTA(E)}. When the lengthier procedure is determined to be inappropriate based on the determined value, the results of the lengthier process can be discarded. Otherwise, the lengthier process, already in progress, is continued.

REFERENCES:
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4639887 (1987-01-01), Farmwald
patent: 4644490 (1987-02-01), Kobayashi et al.
Bidermann et al., "The MicroVAX 78132 Floating Point Chip", Digital Technical Journal, No. 2, Mar. 1986, pp. 24-36.

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