Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1998-04-20
2000-10-17
Malzahn, David H.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
712211, G06F 930
Patent
active
061345733
ABSTRACT:
An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.
REFERENCES:
patent: 4812989 (1989-03-01), Maier et al.
patent: 4961162 (1990-10-01), Nguyenphu et al.
patent: 5070475 (1991-12-01), Normoyle et al.
patent: 5121351 (1992-06-01), Shirakawa et al.
patent: 5301137 (1994-04-01), Matsuo et al.
patent: 5761105 (1998-06-01), Goddard et al.
patent: 5813045 (1998-09-01), Mahalingaiah et al.
patent: 5828873 (1998-10-01), Lynch
Henry G. Glenn
Loper, Jr. Albert J.
Parks Terry
Huffman James W.
Huffman Richard K.
IP-First L.L.C.
Malzahn David H.
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