Apparatus and method for a wafer level chip scale package...

Details Apparatus and method for a wafer level chip scale package... Apparatus and method for a wafer level chip scale package...

2005-07-12

2005-07-12

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S114000, C438S465000, C257S778000

Reexamination Certificate

active

06916688

ABSTRACT:
A flip chip semiconductor package with an integral heat sink is disclosed as well as a technique for creating individual heat sinks by applying a conductive layer to the back surface of a wafer containing integrated circuitry before singulation. According to one aspect of the invention, an adhesive layer is applied to the back surface of a semiconductor wafer. A layer of conductive material such as copper is then attached to the back surface of the wafer using the previously applied adhesive. The wafer is then singulated to create individual semiconductor packages with superior heat transfer properties.

REFERENCES:
patent: 4620215 (1986-10-01), Lee
patent: 6649012 (2003-11-01), Masayuki et al.
patent: 2004/0036161 (2004-02-01), Williams et al.
Merriam-Webster's Collegiate Dictionary, 1998, Merriam-Webster, Tenth Edition, 251.
Kelkar et al., “MicroSMD-A Wafer Level Chip Scale Package”, May 2000, IEEE Transactions on Advanced Packaging, vol. 23, No. 2. p. 227-232.
Vikram et al., “Thermally enhanced flip chip packaging arrangement”, U.S. Appl. No. 09/668,031, filed Sep. 21, 2000.

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