Multiplex communications – Wide area network – Packet switching
Patent
1990-12-31
1993-03-16
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 852, 370 856, H04J 302
Patent
active
051950898
ABSTRACT:
A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.
REFERENCES:
patent: 4677616 (1987-06-01), Franklin
patent: 4787033 (1988-11-01), Bomba et al.
patent: 4809269 (1989-02-01), Gulick
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 5058110 (1991-10-01), Beach et al.
patent: 5081622 (1922-01-01), Nassehi et al.
Chang Jung-Herng
Cruz-Rios Jorge
Frailong Jean-Marc
Lee Douglas B.
Liencres Bjorn
Hom Shick
Olms Douglas W.
Sun Microsystems Inc.
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