Pulse or digital communications – Equalizers
Reexamination Certificate
1998-10-02
2002-11-12
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Equalizers
C375S350000, C708S300000, C708S323000
Reexamination Certificate
active
06480534
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the processing of data signals in communication systems and, more particularly, the processing of data signals in equalizer filter circuits. Equalizer filter circuits or adaptive filter circuits are used to compensate for distortion introduced into the channel during the transmission of the data signals. The present invention has particular applicability to modem units.
2. Description of the Prior Art
Referring to
FIG. 1
, a block diagram of a modem unit
10
, according to the prior art, is shown. INPUT data signals, typically transmitted over a cable, are applied to A/D converter unit
11
of the modem unit
10
. The output signal of A/D converter unit
11
is applied to demodulation unit
12
. The demodulation unit
12
can generate a real signal portion R and an imaginary signal portion I. The signals R and I are applied to equalizer unit
13
. The modified real and imaginary signals R′ and I′, resulting from processing within the equalizer unit, are applied to decision unit
14
. The decision unit
14
provides the OUTPUT signals of modem unit
10
and generates an complex ERROR signal e which is applied to equalizer unit
13
.
Referring to
FIG. 2A
, a block diagram of an equalizer unit
13
, such as would be used in the modem unit
10
of
FIG. 1
for processing a complex INPUT data signals X, is shown. The equalizer unit
13
includes a multiplicity N of stages. Each stage n of the equalizer unit
13
includes a delay line D
n
. The delay lines D
0
−D
N−1
of all of the stages are coupled in series. The output terminal of each delay line D
n
is coupled, in addition to the next sequential delay line D
n+1
, to a multiplier unit M
n
and to an input terminal of update unit U
n
. Each multiplier unit M
n
also receives a coefficient signal C
n
. The coefficient signal is a signal group stored in the update unit U
n
which is updated in update unit U
n
in response to an ERROR signal. An ERROR signal e is generated as a result the processing of each signal group in the decision unit
14
(as shown in FIG.
1
). The product of the signals C
n
and the output signal from delay line D
n
formed in multiplier unit M
n
is applied to adder unit A
n
. The adder unit A
n
receives an output signal from the previous sequential adder unit A
n−1
and the summation of the output signal for multiplier unit M
n
and the output signal from adder unit A
n−1
is applied to the next sequential adder unit A
n+1
. For a series of N delay lines, the input signal X is applied to delay line D
0
and the output signal X′ is applied to the output terminal of adder unit A
N−1
. The delay line D
0
, shown with dotted lines, is not necessary for the operation of the typical filter, but this element is present in the implementation of the present invention.
The equalizer unit
13
shown in
FIG. 2A
is generally referred to as a direct form of an equalizer filter unit or adaptive filter unit. In
FIG. 2B
, the direct form of an equalizer unit is shown in which the series of adder units A
1
through A
N−1
of
FIG. 2A
is replaced by an inverted adder tree in order to reduce latency required to perform the addition operation. Adder units A
0
through A
N/2
each receive signals from two multiplier units and apply output signals therefrom to adder tree circuit
21
. Two output signals from the adder tree circuit
21
are applied to an adder unit AZ, which in turn has the OUTPUT signal X′ applied to an output terminal thereof. As in
FIG. 1
, the delay line D
0
, shown with dotted lines, is not necessary in the implementation of the equalizer filter unit as illustrated. However, this element is used in the present invention.
In
FIG. 2C
, a transpose form of an equalizer unit is shown in which each stage has a configuration differing from the direct form. Each stage of the transpose form of the equalizer unit includes two delay lines, an update unit, a multiplier unit, and an adder unit. In this configuration, DATA IN signals are applied to each multiplier unit M
n
associated with equalizer unit stage n and to the first delay line D
0
in a series of a adder unit A
n
/delay lines D
n
. The multiplier unit M
n
also has a coefficient value stored in update unit U
n
applied thereto. The input signal is also applied to series of delay lines D′
n
, each delay line being associated with one stage of the n
th
stage equalizer filter unit. The INPUT signal groups are transmitted through the series of delay lines D′
n
, however, the signal groups are transferred in the reverse sequential order from the flow of processed signal groups through the equalizer stages. The update unit U
n
receives output signals from a delay line D′
n
associated with stage n. The output signals from multiplier unit M
n
are applied to an n
th
stage adder unit A
n
. The adder unit A
n
has an output signal from delay D
n
applied thereto and the output signal from adder A
n
is applied to the input terminal of the (n+1)
th
stage delay line D
n+1
. The output signal from delay line D
n+1
is applied to the input terminal of the A
n+1
adder unit associated with the (n+1)
th
equalizer filter unit stage. An ERROR signal e is also applied to update unit U
n
. The output signal from adder A
N−1
is the output signal of the equalizer filter unit. The delay line D
0
, the delay line D′
n−1
and the adder unit A
0
, shown by dotted lines, are not necessary for the normal implementation of an equalizer filter, but are needed in the implementation of the present invention.
The input data signal X has a real part R and an imaginary part I. For each input data signal group, X
i
=R
i
+jI
i
. When k is equal to the number of the latest data signal group to be entered in the equalizer (also referred to as an iteration), then as will be clear to those familiar with equalizer units:
X′
k
=R′+jI′=&Sgr;
(
i=
0
−>N−
1)
C*
i,k
X
k−1
.
and
C
i,k+1
=C
i,k
+&mgr;e*
k
X
k−1
where all the quantities except &mgr; can be complex, * denotes the complex conjugate of the number and e
k
is the error signal generated by the decision unit after X′
k
has been generated by the equalizer unit. As this equation indicates, the multiplier coefficients are updated. This requirement for updating these coefficients provides further complexity in the implementation of the equalizer unit.
In a typical equalizer unit, the number of delay lines N can be large. Because each delay line D
n
is coupled to a multiplier unit M
n
and an adder unit A
n
, the equalizer unit
13
can occupy approximately one half of the area of the silicon chip on which the modem unit
10
has been fabricated.
A need has therefore been felt for apparatus and an associated method to reduce the number of components required to implement a modem unit, and particularly, the equalizer unit portion of the modem unit, in an integrated circuit.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by providing an equalizer unit or adaptive filter unit in which the unit, having N components, is divided into M segments. Of the M segments, only one segment has apparatus for up-dating the coefficients of each equalizer component within the segment. The equalizer unit further includes apparatus for cyclically transferring the data and the coefficient signal groups from one segment to the next consecutive segment. In addition, reconfiguration apparatus couples the segments in such a manner that the data continues to be transferred through the segments of the equalizer unit in the sequence established during an initialization of equalizer unit operation. The equalizer unit therefore reduces the apparatus used in the updating of the coefficients by a factor of approximately 1/M. However, by periodically cycling the coefficients
Gatherer Alan
Tran Hiep Van
Brady III W. James
Ghebretinsae Temesghen
Moore J. Dennis
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Apparatus and method for a reduced component equalizer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for a reduced component equalizer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for a reduced component equalizer circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2939258