Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-10-21
2001-09-04
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S323000
Reexamination Certificate
active
06286021
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the processing of signals in communication systems and, more particularly, to the equalizer circuit units. Equalizer circuits or adaptive filter units are used to compensate for distortion introduced into the channel during the transmission of signals. The present invention has particular applicability to transceiver circuits and modem units.
2. Description of the Prior Art
Referring to
FIG. 1
, a block diagram of a transceiver circuit capable of advantageously using the present invention is shown. INPUT SIGNALS are applied to symbol decoder and side-stream descrambler unit
11
. Output signals from the symbol encoder and side-stream scrambler unit
11
are applied to transmitter unit A
15
and to transmitter unit B
13
. The output signals from transmitter unit A
15
are applied to hybrid unit
18
, while the output signals from transmitter unit B
13
are applied to hybrid unit
17
. The output signals from hybrid unit
17
and hybrid unit
18
are applied to cable
19
. Signals from cable
19
are transmitted through hybrid unit
17
to receiver unit B
14
and through hybrid unit
18
to receiver unit A
16
. The output signals from receiver unit A
16
and from receiver unit B
14
are applied symbol decoder and side-stream descrambler unit
12
. The output signals from the symbol decoder and side-stream descrambler unit
12
are the OUTPUT SIGNALS from the transceiver.
In the transmitter unit A
15
, the input signals are applied to a digital transmit filter unit
151
. The output signals from the digital transmit filter unit
151
are processed by an digital-to-analog converter unit
152
and applied to an analog transmit filter unit
153
. The output signal of the analog transmit unit
153
is the output signal of the transmitter A
15
which is applied to a hybrid unit
18
. The transmitter B
13
is implemented in a similar manner.
With respect to the receiver A
16
, the output signals from the hybrid unit
18
are applied to a VGA unit
169
. The output signals from the VGA unit
169
are processed by an analog receive filter unit
168
and applied to an analog-to-digital converter unit
167
. Output signals from the analog-to-digital converter unit
167
are applied to a digital linear forward equalizer unit
166
and to a gain, timing, control unit
170
. The signals from the digital linear forward equalizer unit
166
are applied to a summation network
165
and to the gain, timing and control unit
170
. The gain, timing and control unit
170
applies control signals to the VGA unit
169
and to the analog-to-digital converter unit
167
. The summation unit
165
also receives signals from an echo canceller unit
161
, from a NEXT canceller unit
162
and from a feedback filter
oise predictor unit
164
. Output signals from the summation unit
165
are applied to a decision unit
163
. The decision unit
163
provides the output signal for receiver A
16
. The output signal from the decision unit
163
is also applied to the feedback filter
oise prediction unit
164
. The decision unit
163
also applies an error signal to the echo canceller unit
161
, NEXT canceller unit
162
, digital linear forward equalizer unit
166
, and feedback filter
oise reduction unit
164
. The echo canceller unit
161
also receives signals which are applied to the transmitter A
15
associated with the receiver A
16
, while the NEXT canceller unit
162
receives an input signal from the transmitter B
13
not associated with the receiver unit A
16
which includes the NEXT canceller unit
162
. The receiver B
13
is implemented in a manner similar to receiver A
16
.
Referring to
FIG. 2
, a block diagram of an adaptive equalizer filter unit
20
, such as would be used to implement the echo canceller unit
161
and the NEXT canceller unit
162
of
FIG. 1
, is shown. The equalizer unit
20
includes a multiplicity N of stages. Each stage n of the equalizer unit
13
includes a delay line D
n
, (the delay line Do is shown with dotted lines because the presence of this delay line is not needed to the operation of filter
20
. The delay lines D
0
-D
N−1
of all of the stages are coupled in series. The output terminal of each delay line D
n
is coupled, in addition to being coupled to the next sequential delay line D
n+1
, to a multiplier unit M
n
associated with the n
th
stage and to an input terminal of update unit U
n
associated with the n
th
stage. Each multiplier unit M
n
also receives a coefficient signal C
n
. The coefficient signal C
n
is a signal group stored in the update unit U
n
which is updated U
n
in response to an ERROR signal e and the output signal of delay line D
n
. An ERROR signal e is generated as a result of each signal group processed in the decision unit shown in FIG.
1
. The product of the signals C
n
and the output signal from delay line D
n
formed in multiplier unit M
n
is applied to one terminal of adder unit A
m
. The adder unit A
m
also receives an output signal from one of the neighboring filter stages. The adder units A
0
-A
M−1
are the first stage of an adder tree, the remaining adder units would be included in element
29
. The output signals of the adder tree, including the adder units A
0
-A
M−l
and the element
29
, are the DATA OUT signals (X′).
The signals applied to the multiplier unit M
n
of an adaptive or equalizer filter are the following:
X
n
is the output signal from delay line D
n
, and C
n,t+1
is given by the formula C
n,t+1
=C
n,t
+&mgr;e
t
X
n,t−1
Referring to
FIG. 3
, a schematic block diagram of an update unit
30
(U
n
) is shown. The update unit
30
has a multiplier unit
31
which receives the filter constant &mgr;, the error signal e
t
, and the data signal X
n,t
. The product formed by these three quantities are applied to an input terminal of adder unit
33
. Also applied to an input terminal of adder unit
33
is the previously formed coefficient W
n,t−1
stored in register
32
. The output signal of adder unit
33
is the coefficient W
n,t
. The coefficient W
n,t
is applied to multiplier unit M
n
associated with same stage of the adaptive filter unit as the update unit U
n
and the coefficient W
n,t
is applied to register
32
to be used in generating the next coefficient W
n,t+1
.
As will be clear to those skilled in the art, the implementation of the update units U
0
-U
N−1
require a relatively large number of components to implement, each update unit including both a multiplier unit and an adder unit. This apparatus is required in each stage of the adaptive filter.
A need has therefore been felt for apparatus and an associated method to reduce the number of components required to implement an adaptive filter unit and particularly, the update unit thereof.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, replacing the multiplier unit with apparatus for representing the product of the filter constant, the error signal, and data signal with a single logic bit and an associated sign. The output signal or product of the apparatus is then applied to a counter unit. The counter unit accumulates the signed product logic bits, i.e., the sum of the signed product bits. This sum of the signed product bits is the coefficient W
n,t
, and the next signal product bit added thereto generates the coefficient W
n,t+1
. In order to prevent an overflow of the counter, a logic bit is periodically subtracted from the accumulated sum.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.
REFERENCES:
patent: 5768313 (1998-06-01), Kuribayashi
patent: 5805481 (1998-09-01), Raghunath
patent: 5933452 (1999-08-01), Eun
patent: 5937007 (1999-08-01), Raghunath
patent: 6108681 (2000-08-01), Wittig et al.
patent: 6151614 (2000-11-01), Ikeda
Gu Richard X.
Tran Hiep V.
Brady III W. James
Malzahn David H.
Moore J. Dennis
Telecky Frederick J.
Texas Instruments Incorporated
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