Telephonic communications – Supervisory or control line signaling – Using line or loop condition detection
Reexamination Certificate
2000-11-06
2004-04-27
Nguyen, Duc (Department: 2643)
Telephonic communications
Supervisory or control line signaling
Using line or loop condition detection
C379S406010, C379S387020, C379S398000, C379S402000, C379S416000, C379S399010, C375S232000, C375S220000, C375S238000, C375S288000, C370S493000
Reexamination Certificate
active
06728368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a Class-D line driver, and, and in particular to an improved Class-D line driver for Asymmetric Digital Subscriber Line (ADSL) applications.
2. Background of the Invention
Recently, broadband network applications are increasingly being implemented on digital subscriber lines (DSL), especially on asymmetric digital subscriber lines (ADSL). ADSL has proven to be a preferred technology, since ADSL delivers a good bit rate at low cost to the resident.
ADSL is a new technology that allows more data to be sent over existing copper telephone lines that are used for plain old telephone service (POTS). Unlike cable modem technology, ADSL does not require any costly improvements to the telephone lines. ADSL supports data rates of approximately 1.5 megabits per second (Mbps) to 9 Mbps when receiving data (known as the downstream rate), and supports data rates of approximately 16 kilobits per second (Kbps) to 640 Kbps when sending data (known as the upstream rate). ADSL requires a modified ADSL modem, but the modifications are minor.
ADSL line coding is DMT (Discrete Multi-Tone). DMT line coding consists of 256 carriers that can individually transmit and receive data. This type of line coding is resistant to channel noise, and individual carriers in the noisy part of the channel can be turned off. However, DMT line code has a high Peak-to-Average Ratio (PAR). The large PAR is due to the fact that the addition of 256 carriers at random creates a random signal with an even larger distribution. The high PAR requires line drivers that can supply large peaks of power on demand. The average PAR for a DMT signal is approximately 5.4.
Almost all current line drivers that are presently used for ADSL are linear line drivers with AB output stages. These types of line drivers have very low power efficiencies. The best prior art linear line driver for ADSL transmission from a Central Office (CO) has approximately a 10% power efficiency, which means it dissipates approximately one watt of power for every 100 milliwatts delivered to the load.
The other major requirements for ADSL line drivers are low noise and low distortion. Since the received signal at a remote office at a long distance from the CO is weak, and the transmitted power is large, any distortion on the part of the line driver will corrupt the received signal.
A typical pulse-width-modulation (“PWM”) type line driver (i.e., the Class-D line driver) includes a comparator circuit coupled to the gates (or bases) of a pair of switching transistors that are coupled in series across a D. C. power source. The transistors are disposed in a conventional push-pull configuration. Reverse current bypass or recovery diodes are also coupled in series across the D. C. power source, and the junction of the diodes is coupled to the junction of the paired transistors. A low-pass filter is coupled to the junction of the paired transistors.
The comparator creates a rectangle-wave PWM signal from a modulating input signal and a triangle-wave carrier signal. The PWM signal is applied to the gates of the switching transistors, causing the transistors to be alternately switched on and off in accordance with the duration of the PWM pulses. The resulting demodulated signal passes through the low-pass filter and is output to a load.
Although highly power efficient compared to linear drivers, conventional Class-D line drivers are subject to output distortion. Class-D line drivers generate output distortion due to a mismatch in the output transistors.
An additional cause of output distortion in conventional Class-D line drivers is pulse amplitude error (i.e., crossover distortion) over the analog cycle of the modulating input signal. Class-D line drivers include a pair of switching transistors and recovery diodes. When an analog input signal passes from a positive to negative half cycle, effective output drive is transferred from one transistor and recovery diode to the other transistor and recovery diode. This transition creates a crossover distortion component in the output waveform resulting from recovery diode over-swings and forward voltage drops of the “on” transistor. Finally, Class-D line driver output is also subject to high-frequency ripple distortion created by the frequency of the carrier signal creating PWM waveforms.
FIG. 1
is a circuit diagram of a conventional Class-D line driver. A typical distortion level for the output of a conventional open loop Class-D line driver is 0.1%, which is not adequate for an ADSL modem application. The signal
102
is an input to the PWM block
104
, which provides an output signal received as an input signal to the gates of transistors
106
and
108
. The output from the drains of transistors
106
and
108
is connected through line
110
to load capacitance
112
and load resistance
114
. The source of transistor
108
is connected to an appropriate bias voltage VDD. Load resistance
114
, load capacitance
112
, and the source of transistor
106
are connected to ground (GND).
FIG. 2
is a circuit diagram of a closed loop Class-D line driver. The signal
102
is an input to subtractor
202
, which outputs a signal to a loop filter
204
that may optionally include a PWM. The output of loop filter
204
provides an output signal received as an input signal to the gates of transistors
106
and
108
. The output signal from the drains of transistors
106
and
108
is connected through line
110
to load capacitance
112
and load resistance
114
. The output signal of transistors
106
and
108
is also a feedback signal subtracted by subtractor
202
. The source of transistor
108
is connected to an appropriate bias voltage VDD. Load resistance
114
, load capacitance
112
, and the source of transistor
106
are connected to ground (GND).
This circuit architecture has the benefit of canceling errors at the line driver output by the feedback loop. This type of circuit architecture can achieve −80 Decibels (dB) total harmonic distortion (THD) at low frequencies less than 20 kilohertz (KHz). This type of circuit architecture can achieve −60 dB at higher frequencies, but this is not adequate for ADSL applications.
Another choice for improving the linearity of the line driver is to use a replica line driver to remove the error.
FIG. 3
is a circuit diagram of a replica line driver to remove the error from a Class-D line driver. The signal
102
is an input to line drivers
302
and
304
. Line driver
302
provides an output signal that is an input signal to a subtractor
306
. The output signal of line driver
304
is an input signal to load resistance
314
and subtractor
308
, which subtracts the original signal
102
. The output signal of subtractor
308
is an input signal to be subtracted from the output of line driver
302
by subtractor
306
. Subtractor
306
provides the output signal to load resistance
312
. Load resistance
312
and load resistance
314
are also connected to ground (GND).
This circuit architecture relies on the matching of the parameters of the line drivers to cancel errors in the output. Matching of the line driver parameters is a difficult task, especially during large transient signals. Improvements on the lower frequency band are possible with this circuit architecture, but as the frequency of the input signal increases, this matching becomes less accurate. Parameters such as cross-over distortion are very difficult to cancel with this circuit architecture. Switch synchronization is also not possible for Class-D line drivers.
Another choice for improving the linearity of the line driver is to use analog adaptive filters to match the impedance characteristic of the line to the impedance of the line driver.
FIG. 4
is a circuit diagram of a Class-D line driver with an analog adaptive filter
404
. The signal
102
is an input to line driver
402
. Line driver
402
provides an output signal that is an input signal to termination resistor
406
and to analog adaptive filter
404
, b
Centillium Communications Inc.
Fenwick & West LLP
Jamal Alexander
Nguyen Duc
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