Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2000-02-16
2001-05-22
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S016000, C331S017000, C331S018000, C331SDIG002, C331S00100A, C327S156000, C327S157000, C327S159000
Reexamination Certificate
active
06236278
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to Phase Locked Loops (“PLL's”), and in particular, to a PLL with a fast lock time.
BACKGROUND OF THE INVENTION
Phase Locked Loops (“PLL's”) are systems which allow different signals in different systems to track with one another. One application of a PLL is in digital communication systems. In digital communication systems, the receiving system must be able generate the various frequencies necessary for processing various received signals. For example, a receiving system must be able to synthesize a specific frequency for mixing down the received signals. To accomplish this, a reference frequency is applied to the input of a PLL and a system division ratio of the PLL is set so that the output is some scaled up factor of the input. One problem common to all PLL's is that the output frequency of the PLL system will require a certain amount of time to lock up to a given input frequency. This is known as the lock time. The lock time of a PLL is highly non-linear and very difficult to control. It is desirable to reduce the lock time as much as possible so as to reduce the amount of time the system must wait for the PLL to lock.
Frequency synthesis using a PLL is well known in the art. One example of a prior art PLL frequency synthesizer is shown in FIG.
1
. The PLL
100
of
FIG. 1
includes a phase detector (“PD”)
110
, a loop filter
120
, a voltage controlled oscillator (“VCO”)
130
, a reference divider
101
having a divider ratio of R, and a feedback divider
102
having a divider ratio of B. The PLL
100
of
FIG. 1
is known as an Integer Divider because the frequency at the output is an integer multiple of the frequency at the input of the phase detector. A fixed reference signal Fref is transmitted to the reference divider
101
and then to one input of the Phase Detector. The output of the VCO is divided by the feedback divider and input to the other input of the Phase Detector. Assuming the system is locked the following equation is satisfied:
F1=F2
F1=Fref/R
F2=Fout/B
and
Fout=Fref (B/R)
By way of example, if Fref=10 Mhz, R=100, and B=5, then
Fout=500 kHz
Thus it can be seen that Fout will be some integer fraction of the reference frequency Fref.
Another example of a prior art PLL frequency synthesizer is shown in FIG.
2
. The PLL
200
of
FIG. 2
includes a phase detector (“PD”)
210
, a loop filter
220
, a voltage controlled oscillator (“VCO”)
230
, a reference divider
201
having a divider ratio of R, a feedback divider
202
having a divider ratio of B, and a prescaler divider
203
having a divider ratio of K. The PLL
200
of
FIG. 2
is known as an Integer Divider with Prescaling. A fixed reference signal Fref is transmitted to the reference divider
201
and then to one input of the phase detector. The output of the VCO is divided by the prescaler divider and the feedback divider, and applied to the other input of the phase detector. Again, assuming the system is locked the following equation is satisfied:
F1=F2
F1=Fref/R
F2=F3/B
F3=Fout/K
and
Fout=Fref*K*(B/R)
Therefore, with prescaling, if Fref=10 Mhz, R=100, B=5, K=10, then
Fout=5 MHz
Thus it can be seen that Fout will be some integer fraction of the reference frequency Fref multiplied by the prescaler value.
FIG. 3
shows another example of a prior art PLL used for frequency synthesis. The PLL
300
of
FIG. 3
includes a phase detector
340
, a loop filter
350
, a VCO
360
, a reference divider
310
having a divider ratio of R, a feedback divider
320
having a divider ratio of B, an auxiliary divider
325
having a divider ratio of A, and a dual modulus prescaler
330
which can be configured to have a divide ratio of either K or K+1. Again the reference frequency is divided down before being applied to the input of the phase detector. The output signal is fed back through the dual modulus prescaler which feeds a signal to both the feedback divider and the auxiliary divider. The output of the feedback divider is applied to the other input of the phase detector.
To understand the operation of the PLL
300
of
FIG. 3
by way of example, assume that both the feedback divider and auxiliary divider are DOWN counters, referred to here as B-counter and A-counter respectively. The output of the B-counter is transmitted to the input of the phase detector, and additionally, over LOAD line
301
to the load inputs of both the A-counter and B-counter. Therefore, every time the B-counter counts to zero and outputs a pulse, it will reset both the B-counter and the A-counter to their initial values. The dual modulus prescaler
330
is a divider which can divide the output, Fout, by two different integer values (in this case K and K+1) in accordance with the Prescaler Control line
302
from the A-counter. Assuming the system is locked and the B-counter has just counted down to zero and output a pulse to an input of the phase detector as well as reset the B-counter and A-counter, the signal Fout at the VCO output will be received by the dual modulus prescaler. Initially, the prescaler will divide the VCO output, Fout, by K+1 and the prescaler output will begin to supply pulses to both the B-counter and A-counter, causing each to begin to count down. When the A-counter reaches zero, a signal is transmitted over the Prescaler Control line which causes the dual modulus prescaler to reconfigure itself to stop dividing by K+1 and begin dividing by K. Thereafter, the prescaler will divide the output, Fout, by K and the prescaler output will cause the B-counter to continue to count down until it reaches zero. When the B-counter reaches zero, it outputs another pulse to the input of the phase detector. This pulse also causes the A-counter and B-counter to reset. Therefore, it can be seen that for every pulse, Npd, at the input of the phase detector, there will be Ntot pulses at the output of the VCO. Ntot can be determined by noting that while the A-counter is counting down the prescaler is dividing by K+1. Therefore, the total number of pulses at the VCO output required for the A-counter to count down to zero is A(K+1). Thereafter, the prescaler divides by K, so the total number of pulses at the VCO output required for the B-counter to finish its count down to zero is (B−A)(K) (note: the B-counter and A-counter were counting down together). Therefore, the total number of pulses at the output of the VCO, Ntot, is given by:
Ntot=A(K+1)+(B−A) K For one pulse, Npd, into the phase detector.
Ntot=A+BK
or in terms of the period,
Tpd=Tout (A+BK)
Tpd=1/F1 and Tout=1/Fout
Fout=F1 (A+BK)
Therefore, the following equations are satisfied:
F1=Fref/R=F2=F3/B
F3=Fout/(K+1) For A cycles (i.e. while A is counting down)
F3=Fout/K For B−A cycles (i.e. while B is counting down after A has finished counting down.
and the VCO output frequency is given by:
Fout=(Fref/R)*(A+BK)
It can be seen that a necessary condition of this system is that the B-counter must contain a value which is equal to or larger than the value contained within the A-counter. It can be seen that other implementations besides DOWN counters could be used to implement the system of FIG.
3
. Therefore, a more generic condition for the system is that the auxiliary divider must signal the prescaler and become inactive before the B-divider. This type of PLL frequency synthesizer is called a dual modulus prescaler integer PLL.
In many systems it is advantageous to synthesize a frequency which is a non-integer multiple or fraction of a reference frequency. Such frequency synthesizers are called fractional frequency synthesizers and achieve faster phase lock since the reference frequency can be increased. An example of a prior art PLL used as a fractional frequency synthesizer is shown in FIG.
4
A. The fractional frequen
Baker & McKenzie
Mis David
National Semiconductor Corporation
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