Apparatus and method for a dynamic random access architecture

Details Apparatus and method for a dynamic random access architecture Apparatus and method for a dynamic random access architecture

1997-09-04

1999-06-08

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518904, 36518521, 365196, 365233, G11C 800

Patent

active

059109262

ABSTRACT:
A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.

REFERENCES:
patent: 5307321 (1994-04-01), Sasai et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5412613 (1995-05-01), Galbi et al.
patent: 5610871 (1997-03-01), Hidaka
patent: 5703829 (1997-12-01), Suzuki et al.

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