Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-09-10
2004-03-23
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S156000
Reexamination Certificate
active
06710731
ABSTRACT:
FIELD OF INVENTION
The invention relates to an electronic circuit and its operational method, and particularly to a digital-to-analog converter architecture that guarantees monotonicity and partial compensation for integral non-linearity.
BACKGROUND OF INVENTION
Digital-to-analog converters (DAC) process digital signals into analog signals. In particular, high-resolution Nyquist-rate DACs are difficult to achieve, and are required in a wide range of areas, including sensor interfaces, biomedical electronics, and communications. Conventional DAC architectures include resistor string converters, binary scaled converters, and hybrid converters. It is desirable to provide a high-performance DAC architecture, particularly using complementary metal oxide semiconductor (CMOS), bipolar, bi-CMOS, gallium arsenide (GaAs), and other semiconductor process. It would be especially desirable to provide a converter design having guaranteed monotonicity, particularly wherein such converter has a differential nonlinearity (DNL) of +/−1 least significant bit (LSB).
SUMMARY OF INVENTION
The invention is embodied in an apparatus and a method for digital-to-analog conversion, particularly using an architecture that guarantees monotonicity and partial compensation for integral non-linearity. Preferred DAC includes two stages separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, VREFH, and the other end at reference low voltage, VREFL; and the second stage is a multi-bit resistor string converter.
Moreover, a buffer amplifier input is used between two resistors of the 1-bit front-end, and the output is coupled to one end of the multi-bit resistor string. Thus, when the most significant bit (MSB) is a 0, the other end of the multi-bit resistor string is at VREFL via a pass gate. When the MSB is a 1, the end that was connected to VREFL is connected to VREFH via another pass gate.
The architecture relieves matching accuracy necessary for the 1-bit front end. The mismatch of resistors is compensated by varying buffer amplifier offset voltage and ensuring amplifier output is halfway between reference voltages. This architecture improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. A buffer amplifier at the output of the second stage of the DAC controls INL error by varying offset voltage.
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Kaplish Anurag
Tabler John A.
Fernandez & Associates LLP
Mai Lam
Summit Microelectronics Inc.
Tokar Michael
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