Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-05-19
2001-02-27
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S163000
Reexamination Certificate
active
06194927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electronic circuits and, more particularly, to logic circuits that generate signals in response to coincident edges of processor clock signals and bus clock signals. A data processing system typically includes a single bus clock controlling activity on the system bus and multiple processor clocks controlling internal activity in the processor components. In order to coordinate certain intercomponent activity, such as the transfer of data, the processor clocks must be synchronized with the bus clock. This synchronization is typically coordinated by the generation of a signal in the processor component identifying the coincidence of the leading edges (illustrated by rising edges herein) of the bus clock signal and the processor clock signal.
2. Description of the Related Art
In computer systems, the clock controlling the operation of the processor typically has a far higher frequency than the clock that is applied to the processing system bus. For example, in personal computer systems (PCs or Pentium™-compatible processor systems), the processor clock normally generates a clock signal with at least twice the frequency of the bus clock signal. As newer generations of processors become available for personal computing systems, the frequency of the processor clocks tend to exceed the bus clock frequencies by increasingly wide margins. In order to facilitate compatibility between the processor operating frequency and the bus operating frequency, processors are designed such that ratio of the processor clock frequency to the bus clock frequency is a whole integer or a half integer. Table 1 provides typical examples of the processor clock frequency compared to the bus clock frequency.
TABLE 1
RATIO OF THE PROCESSOR CLOCK FREQUENCY
TO THE BUS CLOCK FREQUENCY
Processor Clock
Bus Clock
Frequency
Frequency
Ratio
133 MHz
66 MHz
2
200 MHz
66 MHz
3
233 MHz
66 MHz
3.5
266 MHz
66 MHz
4
300 MHz
66 MHz
4.5
Processors frequently include synchronization circuitry, such as phase-locked loops, for establishing a timing relationship between processor clock frequency and the bus clock frequency. Consequently, when the processor clock frequency to bus clock frequency ratio is a whole integer, each rising edge of the bus clock signal B
CLK
is coincident with a rising edge of the processor clock signal P
CLK
. Referring to
FIG. 1A
, a coincidence circuit
10
for providing the EVENB
CLK
signal, the signal designating the coincidence between the P
CLK
signal and the B
CLK
signal, according to the prior art, is shown. The coincidence circuit
10
includes a flip-flop unit
11
that has P
CLK
signal applied to the D terminal. The B
CLK
signal is applied to the clock terminal of flip-flop
11
. The Q terminal of the flip-flop unit
11
is coupled to the D terminal of flip-flop unit
12
and to a first terminal of logic AND gate
13
. The flip-flop unit
12
has the P
CLK
signals applied to the clock terminal. The Q terminal of flip-flop
12
is coupled to a second, inverting terminal of logic AND gate
13
and is coupled to a reset terminal of flip-flop unit
11
. The output terminal of logic AND gate
13
is coupled to latch unit
14
. The output signal of latch unit
14
is the P
CLK
-B
CLK
leading edge coincident signal EVENB
CLK
. The operation of the coincidence circuit can be understood with reference to FIG.
1
B. In
FIG. 1B
, the relationship of the B
CLK
signal, the P
CLK
signal, and the EVENB
CLK
signal are shown for the configuration wherein the frequency of the P
CLK
signal is 3× the frequency of the B
CLK
signal. The dotted lines indicate the actual coincidence of the B
CLK
and the P
CLK
signals. The leading edge of the EVENB
CLK
signal is delayed half P
CLK
signal cycle and has a signal width of one P
CLK
signal cycle. As will be clear, this circuit relies on the alignment of the B
CLK
and the P
CLK
signal for proper operation. As a practical matter, the circuits that provide these signals are sensitive to noise and to component parameters that prevent the attainment of idealized waveforms. These factors can provide a phase shift in the processing system signals, the phase shift providing uncertainty with respect to the relationship of the leading edges of the signals. Referring to
FIG. 2
, the effect of these factors on the leading edge of the P signal is shown. The uncertainty in the leading edge of the P
CLK
signal as compared to the B
CLK
signal is shown by the shaded area in the P
CLK
signal and is designated as ±&Dgr;. In addition, when the P
CLK
frequency is very much greater than the B
CLK
signal frequency, the half cycle time of P
CLK
signal can approach the magnitude of the phase error &Dgr; and result in a lack of ability to generate accurately the EVENB
CLK
signal. An example of this difficulty is illustrated in FIG.
3
. The leading edge of the B
CLK
signal leads the P
CLK
signal by a sufficient time that the flip-flop unit
11
of
FIG. 1
is unable to sample properly the P
CLK
signal. At low P
CLK
frequencies, the inability to generate the EVENB
CLK
signal is less likely to occur because the P
CLK
cycle time is long enough to compensate for a relative phase shift between the B
CLK
signal and the P
CLK
signal. At high frequencies, the circuit is more prone to failure because the skew between the signals will remain fixed (in the best situation) as the P
CLK
cycle will become smaller.
In addition, when the processor clock signal frequency to bus clock signal frequency ratio is a half integer, then the alternating rising signal edges (such as even leading signal edges) of the bus clock signal are coincident with leading edges of the processor clock signal, and the remaining signal rising edges (such as the odd signal leading edges) of the bus clock signal are not coincident with signal rising edges of the processor clock signal.
SUMMARY OF THE INVENTION
A need has therefore been felt for a circuit generating the EVENB
CLK
signal having the feature that a logic signal or logic signals is/are generated in response to substantially coincident rising edges of a processor clock signal P
CLK
and a bus clock signal B
CLK
over a range of processor clock/bus clock frequency ratios that include whole integers and half integers. The EVENB
CLK
circuit would further have the feature that the circuit is not sensitive to the phase differences between the P
CLK
signal and the B
CLK
signal and would function at high values of the P
CLK
/B
CLK
signal frequency ratios.
The aforementioned and other features are accomplished, according to the present invention, in a processing system wherein the bus clock signal B
CLK
, having a frequency of F is applied to a phase-locked loop unit, the phase-locked loop unit being configured to generate processor clock signal P
CLK
having a frequency of N×F, where N is an integer or half integer greater than or equal to two. An EVENB
CLK
signal generating unit or coincidence unit has applied thereto a P
CLK
signal and a signal having an established phase relationship with the B
CLK
signal. In the preferred embodiment, the P
CLK
/M signal, the output signal from a divide-by-M unit (M=2N) in the phase-locked loop that is applied to the phase detector unit of the phase-locked loop, is applied to coincidence unit. When the P
CLK
signal and the P
CLK
/M signal are coincident, a rising edge of the P
CLK
signal is coincident with a rising edge of the B
CLK
signal and the EVENB
CLK
signal is generated. However, when N is a integer, a leading edge of the P
CLK
signal is coincident with a leading edge of B
CLK
signal between the generation of consecutive P
CLK
/M signals. In order to generate an EVENB
CLK
signal in the absence of a P
CLK
/M signal, each P
CLK
/M signal generates a signal in delay apparatus, a delayed signal being provided by the delay apparatus with an appropriate delay to substitute for the missing P
CLK
/M signal.
REFERENCES:
patent: 5561390 (1996-10-01), Hiiragizawa
patent: 5731723 (199
Ben-Meir Amos
Crowley Matthew P.
Advanced Micro Devices , Inc.
Nguyen Linh
Skjerven Morrill & MacPherson LLP
Tran Toan
Wisor Rita
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