Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2001-04-03
2002-06-18
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S119000, C327S173000, C331S053000, C708S103000
Reexamination Certificate
active
06407596
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a apparatus and method for a delay generator. In particular, the present invention relates to a apparatus and method that generates a delay in order to subdivide a clock period.
BACKGROUND OF THE INVENTION
A master clock signal is often used to generate timing signals in integrated circuits. The master clock provides two well-defined edges, a rising edge and falling edge. The rising edge and falling edge define the clock high (logic “1”) and clock low (logic “0”) time. The clock high and clock low time are each approximately one half of a full clock period in duration. Certain circuit functions may require a clock signal that is faster than the half-period of the master clock signal. These circuit functions are clocked at a higher rate by creating additional signals from the master clock signal. A fast clock signal can be created by delaying one of the master clock signal's edges using a delay circuit. The delayed clock edge may be combined with the master clock signal to create a higher frequency clock signal.
Fixed delay elements are one method for creating a delay in the master clock edge. Fixed delay elements include inverter chains and/or RC time circuits. A high frequency clock can be generated by combining the delayed clock signal with the original clock signal. Fixed delay elements provide a delay that does not change with variations in the master clock period. The delay time of the fixed delay elements is affected by process changes, power supply variations, and temperature variations.
Delay-Lock Loops (DLL's) and Phase-Lock Loops (PLL's) are another method for creating a delay in the master clock edge. A DLL or PLL includes a Voltage-Controlled Oscillator (VCO) or Voltage-Controlled Delay element (VCDL), a phase and/or frequency detector, charge-pump, and loop filter.
Synchronous Delay Lines (SDL) are yet another method for creating a delay in the master clock edge. To reliably subdivide the period of the master clock the SDL explicitly uses feedback control. Negative feedback control of the SDL reduces sensitivity to supply-voltage variations, temperature changes, and processing variations.
SUMMARY OF THE INVENTION
Briefly stated, in accordance with the present invention an electronic circuit generates additional clock edges from a reference clock signal utilizing switch-capacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.
According to a feature of the invention, an apparatus for generating an output signal from a reference clock signal, includes: a first capacitance circuit, a second capacitance circuit, and a charge circuit that charges the first capacitance circuit in response to a first control signal. A discharge circuit discharges the second capacitance circuit in response to a second control signal. A switch circuit transfers at least a portion of a charge stored in the first capacitance circuit to the second capacitance circuit in response to a third control signal. A detector circuit produces a trigger output signal in response to a potential in the second capacitance circuit. A control logic circuit generates the first, second and third control signals in response to the reference clock signal and the trigger output signal. The control logic circuit also generates the output signal in response to the trigger output signal and the reference clock signal.
According to another feature of the invention, a method of generating a high frequency clock signal from a reference clock signal includes: charging a capacitance circuit over a time interval, transferring a portion of a charge from the capacitance circuit to another capacitance circuit over another time interval, discharging one of the capacitance circuits over yet another time interval, detecting a potential in one of the capacitance circuits to produce a logic output, and combining the logic output with the reference clock signal to generate the high frequency clock.
According to yet another feature of the invention, an apparatus for generating a high frequency clock signal from a reference clock signal includes: a charge storage means, a means for producing a current, a means for selectively coupling the current to the charge storage means during a time interval, another charge storage means, a means for selectively coupling a portion of a charge stored in the charge storage means to the another charge storage means during another time interval, a means for producing a logic signal by detecting a potential of a node in one of the charge storage means and the another charge storage means, and a means for selectively discharging the node that is responsive to the logic signal. The apparatus may also include a means for producing the high frequency clock signal responsive to the logic signal.
REFERENCES:
patent: 6121811 (2000-09-01), Scott et al.
Tursi et al., “A 100 MSPS 8-b CMOS Subranging ADC with parametric operation from 3.8V down to 2.2V, ” CICC, May 2000, 4 pages.*
Bazes, “A Novel Precision MOS Synchronous Delay Line,”IEEE Journal of Solid-State Circuits, Dec. 1985, pp. 1265-1271.
Watanabe et al., “A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM's,”IEEE Journal of Solid-State Circuits, Aug. 1989, pp. 905-910.
Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,”IEEE Journal of Solid-State Circuits, Nov. 1996, pp. 1723-1732.
Taft et al., “A 100-MSPS 8-b CMOS Subranging ADC with parametric operation from 3.8 V down to 2.2 V,”CICC, May 2000, 4 pages.
Papalias Chris William
Taft Robert Callaghan
Branch John W.
Callahan Timothy P.
Merchant & Gould P,C,
National Semiconductor Corporation
Nguyen Minh
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