Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2003-03-26
2004-07-27
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S404000, C327S546000
Reexamination Certificate
active
06768351
ABSTRACT:
FIELD OF INVENTION
The present invention relates to semiconductor technology, and more particularly, to compensation of drain current degradation of P-type Metal Oxide Semi-conductor (“pMOS”) transistors.
BACKGROUND
Drain current degradation in pMOS transistors may be caused by temperature and electric field induced gate oxide changes. An example of such changes is pMOS bias temperature degradation (“PBT”). Drain current degradation occurs over the operating life of a pMOS transistor. PMOS transistors are stressed by vertical electric fields, unlike n-type transistors (“nMOS”), pMOS degradation occurs during such stress regardless of whether drain current flows or not.
FIG. 1
shows a cross-section of a pMOS transistor. The substrate
140
of the pMOS transistor is biased with a positive voltage. When a negative voltage is applied to the gate
110
of the transistor, a vertical electric field is created across the gate oxide. The vertical electric field stresses the gate oxide
150
and causes an increase in Vtp which in turn causes the drain current
160
flowing throw the pMOS transistor to degrade over time. Such drain current degradation is commonly known as the aging of a pMOS transistor.
The effect of drain current degradation of a pMOS transistor over time is shown in FIG.
2
. In
FIG. 2
, a graph of the drain current of a pMOS transistor against the voltage across the gate and source of the pMOS transistor (I-V curve) is shown. Curve
210
is the initial I-V curve of a pMOS transistor. The initial threshold voltage of the pMOS is Vtp
215
. Over time, due to stress on the gate oxide of the pMOS transistor, the threshold voltage of the pMOS transistor shifts to Vtp'
225
, which is more negative than the initial threshold voltage Vtp
215
. Therefore, after aging, a more negative voltage across the gate and source of the pMOS is required to invert the channel of the aged pMOS transistor. In other words, the I-V curve of the pMOS transistor is shifted left over time and by temperature as indicated by the curve
220
in FIG.
2
A. The drain current degradation is the drop in drain current, &Dgr;I
d
230
in FIG.
2
A.
The pMOS transistors driving an input/output may be particularly susceptible to drain current degradation since their drain terminals may be connected to a cable internal or external to a computer system, stress could be unintentionally applied to the pMOS drain as a result of a mechanical failure due to an object rolling over the cable or someone repeatedly stepping onto the cable creating a short circuit. High voltages at the input/output may go to the drain of the pMOS transistor driving the input/output. Coupled with the negative voltage applied onto the gate of the pMOS transistor, the high voltage creates a strong electric field stressing the gate oxide of the pMOS transistor. Over time, and especially at elevated temperature, the stress on the gate oxide of the pMOS transistor causes drain current degradation in the pMOS transistor.
To alleviate the problem of pMOS drain current degradation, circuits using external components not subject to aging, such as precision resistors, may be used to calibrate schemes intended to compensate for drain current variations of the pMOS transistors in an input/output device. Ordinarily, the external components are mounted on a printed circuit board. An interface using these methods must include extra signal paths and firmware specific to the method for calibration and operation. Adding these external components to an interface device is very expensive and alters the form and function of the interface. In addition, a clock signal from the system in which the interface is used must be provided to facilitate the external components to calibrate and compensate for drain current degradation.
REFERENCES:
patent: 6218863 (2001-04-01), Hsu et al.
patent: 6587994 (2003-07-01), Yamaji
patent: 6661250 (2003-12-01), Kim et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Zweizig Jeffrey
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