Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-12-30
2001-05-29
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S163000
Reexamination Certificate
active
06239734
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to an analog-to-digital converting apparatus and an analog-to-digital converting method. The analog-to-digital converting apparatus compares an analog input signal to a number of reference voltages to provide digital values.
2. Description of the Related Arts
FIG. 1
shows a simple and fast flash type of analog-to-digital converter. The analog-to-digital converter comprises a voltage generator
10
for generating a number of reference voltages, and a comparing unit
12
for comparing an analog input signal to each of the reference voltages. The voltage generator
10
includes a number of registers serially coupled between a voltage source and the ground. The voltage applied at each node of the registers is provided to the comparing unit
12
as the reference voltages. The comparing unit
12
includes a number of comparators (COM). Each of the comparators receives each reference voltage of the voltage generator
10
at a positive terminal (+) and receives the analog signal at a negative terminal (−). After receiving, each of the comparators compares the voltage of the input signal to each of the reference voltages. In case that the voltage of the input signal is greater than one of the reference voltages, one of the comparators outputs “1” signal, otherwise, the comparator outputs “0” signal.
The flash type of N-bit analog-to-digital converter generates the reference voltages by using 2
N
registers. Each outcome of the comparisons between each of the reference voltages and the analog input signal is outputted by using (2
N−1
−1) number of the comparators. The output signal is performed by a priority decoding which provides the final digital signal corresponding to the analog input.
The flash type of analog-to-digital converter is capable of converting an analog signal to a digital signal at one time however, it increases the complexity of the hardware. In order to decrease the complexity of the hardware, a SAR(Successive Approximation Register) type of analog-to-digital converter is suggested.
FIG. 2
is the SAR type of analog-to-digital converter. The SAR type of the analog-to-digital converter comprises a comparator
20
, a digital-to-analog converter
21
and a converting controller
22
which has a special register (SAR)
24
and a controller
23
for controlling the SAR
24
.
FIG. 3
shows the total converting algorithm of the SAR type of analog-to-digital converter. First, in step
30
, a parameter I for counting the bits of the SAR register
24
is set to “1”, and then SAR[
1
:N] is set to “0”. In step
32
, I bits of the SAR register
24
is set to “1” (SAR=1000 . . . 000). In step
34
, when the value of the SAR register
24
is converted from the digital to the analog, the analog value of the SAR register
24
is compared to the analog input signal. In step
36
, if the analog input signal is less than the analog value of the SAR register, the I-bit of the SAR register is cleared to “0” (SAR=0000 . . . 000). If the analog input signal is larger than or equal to the analog value of the SAR register in step
34
, the value of the SAR register is not changed and step
34
is going to a step
38
. In step
38
, the parameter I is compared to another parameter N indicating the value of the SAR register
24
, wherein if the parameter I is larger than or equal to the parameter N, the process is ended, otherwise the process is going to step
32
. In this point, in case that the analog input signal is lager than or equal to the SAR register
24
, the comparator
20
outputs “1”. Otherwise, in case that the analog input signal is less than the SAR register
24
, the comparator
20
outputs “0”. This process is continued to the Nth bit during N cycles, and then the final stored value of the SAR register
24
is the final converted value of the analog-to-digital conversion.
FIG. 4
shows an example operation of 6-bit SAR analog-to-digital converter. There is shown the change of the value of the SAR register corresponding to the converting cycles in case that the analog input signal is 110011. The output signal of the comparator
20
from the first to the sixth cycle is changed as follows: “1”→“1”→“0”→“0”→“1”→“1”. And the value of the SAR register
24
is changed as follows: “100000”→“110000”→“110000”→“110000”→“110010”→“110011”.
Detailed descriptions of above changes are as follows. In step
30
, the parameter I is set to “1”. After initializing the SAR register
24
, in step
32
, the value of the SAR register is set to “100000”. In step
34
, since the value of the analog input signal “110011” is lager than the value of the SAR register “100000”, the value of the SAR register is not changed. In step
38
and step
39
, since the parameter I is “1” and the value of N is “6”, the value of I is changed to “2” and the process is going to step
32
. In step
32
, the value of the SAR register is set to “110000”. In step
34
, since the value of the analog input signal “110011” is lager than the value of the SAR register “110000”, the value of the SAR register is not changed. In step
38
and step
39
, since the parameter I is “2” and the value of N is “6”, the value of I is changed to “3” and the process is going to step
32
. In step
32
, the value of the SAR register is set to “111000”. In step
34
, since the value of the analog input signal “110011” is less than the value of the SAR register “111000”, SAR[
3
] is cleared to zero. Therefore, the value of the SAR register is changed to “110000”. In step
38
and step
39
, since the parameter I is “3” and the value of N is “6”, the value of I is changed to “4” and the process is going to step
32
. In step
32
, the value of the SAR register is set to “110100”. In step
34
, since the value of the analog input signal “110011” is less than the value of the SAR register “110100”, SAR[
4
] is cleared to zero. Therefore, the value of the SAR register is changed to “110000”. In step
38
and step
39
, since the parameter I is “4” and the value of N is “6”, the value of I is changed to “5” and the process is going to step
32
. In step
32
, the value of the SAR register is set to “110010”. In step
34
, since the value of the analog input signal “110011” is lager than the value of the SAR register “110010”, the value of the SAR register is not changed. In step
38
and step
39
, since the parameter I is “5” and the value of N is “6”, the value of I is changed to “6” and the process is going to step
32
. In step
32
, the value of the SAR register is set to “110011”. In step
34
, since the value of the analog input signal “110011” is equal to the value of the SAR register “110011”, the value of the SAR register is not changed. In step
38
and step
39
, since the parameter I is “6” and the value of N is “6”, the process is ended.
In the prior art, since the analog-to-digital converter employs only one comparator, the converting time requires N cycles so that the processing speed of the converter is decreased.
SUMMARY OF THE INVENTION
Therefore, the present invention is to provide an analog-to-digital converter capable of increasing the processing speed of the converter by using a number of SAR registers.
According to the present invention, the analog-to-digital converter, comprises: means for storing a first, a second and a third digital signals, respectively; means for controlling conversions of two bits contained in one of the digital signals stored at the storing means in response to a first, a second and a third comparing signals; means, having a first, a second and a third digital-to-analog converters, for converting the first, the second and the third digital signals by using each of the digital-to-analog converters to provide a first, a second and a third analog reference signals; and means for comparing each of the analog reference signals to an analog input signal which is to be converted, to provide said first, said second and said th
Ahn Mun Weon
Bae Jong Hong
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Wamsley Patrick
LandOfFree
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