Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-09-08
2001-12-11
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S670000, C708S707000
Reexamination Certificate
active
06330581
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to microprocessors and, more particularly, to an apparatus and a method for address generation in an ALU (Arithmetic Logic Unit) in a microprocessor.
BACKGROUND OF THE INVENTION
A microprocessor typically includes a memory management subsystem that provides segmentation and paging. For example, the well known Intel X86™ /Pentium™ microprocessors include a memory management subsystem that provides a segment translator and a page translator.
Address generation in a microprocessor that implements segmentation and paging typically requires adding a constant or a displacement, a (logical) base, and a segment base to generate an address. For example, a typical address generation unit
100
is shown in prior art FIG.
1
. Address generation unit
100
uses a 2-to-1 multiplexer to select either a constant or a displacement and then adds the multiplexer output, a (logical) base, and a segment base to generate a 32-bit address. In particular, prior art address generation unit
100
generates the lower 16 bits (bits [
15
:
0
]) of the 32-bit address by selecting either a constant or a displacement in a 16-bit multiplexer
110
, adding the output value of multiplexer
110
to the lower 16 bits of the (logical) base in a 16-bit carry-propagate adder
102
, and then adding the output value of 16-bit carry-propagate adder
102
and a lower 16 bits of the segment base using a 16-bit carry-propagate adder
104
. Prior art address generation unit
100
generates the upper 16 bits (bits [
31
:
16
]) of the 32-bit address by selecting either a constant or a displacement in a 16-bit multiplexer
112
, adding the output value of multiplexer
112
to the upper 16 bits of the base using a 16-bit carry-propagate adder
106
, which receives a carry-in value from a carry-out value of 16-bit carry-propagate adder
102
, clearing the output value of 16-bit carry-propagate adder
106
using 16-bit AND-gate
114
, and then adding the output of 16-bit AND-gate
114
and an upper 16 bits of the segment base using a 16-bit carry-propagate adder
108
, which receives a carry-in value from a carry-out value of 16-bit carry-propagate adder
104
. The clearing or zeroing of the 16-bit carry-propagate adder
106
is used during 16-bit mode, in which only the lower 16 bits of the constant or displacement and the (logical) base affect the 32-bit address output. In 32-bit mode, the 16-bit AND-gate
114
output is equal to the 16-bit carry-propagate adder
106
output allowing all 32 bits of the constant or displacement and the (logical) base to affect the 32-bit address output. Accordingly, prior art address generation unit
100
generates the 32-bit address using 16-bit carry-propagate adders
102
,
104
,
106
, and
108
.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and a method for address generation. In particular, the present invention provides a cost-effective and efficient apparatus and method for address generation in a microprocessor that includes a memory management subsystem that provides segmentation and paging.
In one embodiment, an apparatus includes a 32-bit 2-to-1 multiplexer for selecting either a constant or a displacement, a first 16-bit carry-propagate adder and a second 16-bit carry-propagate adder for adding a lower 16 bits (bits [
15
:
0
]) of the multiplexer output, a lower 16 bits of a segment base, and a lower 16 bits of a (logical) base to generate a lower 16 bits of a 32-bit address. In this embodiment, the apparatus also includes a first 16-bit carry-propagate adder, a second 16-bit carry-propagate adder, a third 16-bit carry-propagate adder, a 16-bit AND-gate, and a 16-bit carry-tree for generating an upper 16 bits (bits [
31
:
16
]) of the 32-bit address.
In one embodiment, the apparatus also includes a TLB (Translation Lookaside Buffer) that uses an upper 4 bits of the lower 16 bits (bits [
15
:
12
]) of the 32-bit address for a TLB lookup (or matching) operation. Further, the apparatus also includes a comparator that compares the upper 16 bits (bits [
31
:
16
]) of the 32-bit address to an output of the TLB for determining a TLB hit or miss.
In one embodiment, a method includes adding a lower 16 bits of a constant or displacement, a lower 16 bits of a segment base, and a lower 16 bits of a base using a first 16-bit carry-propagate adder and a second 16-bit carry-propagate adder to generate a lower 16 bits of a 32-bit address. In this embodiment, the method also includes generating an upper 16 bits of the 32-bit address using a third 16-bit carry-propagate adder and a fourth 16-bit carry-propagate adder.
In one embodiment, the method also includes transmitting an upper 4 bits of the lower 16 bits of the 32-bit address to a TLB, and transmitting a lower 12-bits of the lower 16 bits of the 32-bit address to a 12-bit page offset (e.g., the 12-bit page offset, which represents an offset within a page, can be used to provide the lower 12 bits (bits [
11
:
0
]) of a 32-bit physical address). Further, the method includes transmitting the upper 16 bits of the 32-bit address to a comparator for comparing the upper 16 bits of the 32-bit address to an output of the TLB for determining a TLB hit or miss.
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.
REFERENCES:
patent: 5351207 (1994-09-01), Girard et al.
patent: 5583806 (1996-12-01), Widigen et al.
patent: 5612911 (1997-03-01), Timko
patent: 5625582 (1997-04-01), Timko
patent: 5961580 (1999-10-01), Mahalingaiah
patent: 6003125 (1999-12-01), Shippy
ATI International SRL
Malzahn David H.
Skjerven Morrill & MacPherson LLP
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