Aperture generating circuit for a multiplying delay-locked loop

Details Aperture generating circuit for a multiplying delay-locked loop Aperture generating circuit for a multiplying delay-locked loop

2011-08-09

2011-08-09

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S153000, C327S161000

Reexamination Certificate

active

07994832

ABSTRACT:
A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

REFERENCES:
patent: 6617936 (2003-09-01), Dally et al.
patent: 6952431 (2005-10-01), Dally et al.
patent: 6982579 (2006-01-01), Lee
patent: 7728754 (2010-06-01), Gerfers et al.
patent: 2010/0327925 (2010-12-01), Kapusta et al.

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