APD bias circuit

Details APD bias circuit APD bias circuit

2000-02-18

2003-11-04

Chan, Jason (Department: 2733)

Optical communications

Receiver

C250S2140RC

Reexamination Certificate

active

06643472

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an APD (Avalanche PhotoDiode) bias circuit which stably operates an APD receiving a light signal.
As is known, the multiplication factor of the APD can be controlled by a bias current flowing therein. Thus, the bias voltage is controlled in accordance with the light input level, so that the received signal can be maintained at a given level.
2. Description of the Related Art
FIG. 1
shows an optical receiver
100
, which includes an APD
101
, a bias circuit
102
, an equalizer amplifier
103
, a timing extractor
104
, and a decision making unit
105
. An optical input OPTin from an optical transmission line or the like is applied to the APD
101
. The bias circuit
102
controls the multiplication factor of the APD
101
in accordance with the level of the optical input OPTin.
The output signal of the APD
101
is equalized by the equalizer amplifier
103
. A timing signal corresponding to the bit rate of data is extracted from the equalized signal by the timing extractor
104
, and is output as a clock signal CLKout. The clock signal CLKout is also applied to the decision unit
105
as a decision timing signal. The decision unit
105
makes a level decision and outputs reproduced data DATAout.
FIG. 2
is a circuit diagram of a conventional APD bias circuit, which is related to the APD
101
, the bias circuit
102
, and the equalizer amplifier
103
shown in
FIG. 1. A
voltage V
DD
is applied to the APD
101
via resistors R
1
a
and R
2
a
connected in series. A current I
APD
flowing in the APD
101
and having a magnitude based on the level of the optical input is applied to the equalizer amplifier
103
. A bias control circuit is connected to a node in which the resistors R
1
a
and R
2
a
are connected together. The above bias control circuit includes Vo control circuit
111
, a Vo monitor circuit
112
, an internal stabilized power source
113
, an M
OPT
adjustment unit
114
, a temperature sensor
115
, and a temperature control circuit
116
. Even if the current I
APD
fluctuates due to variations in temperature and the optical input, the Vo control circuit
111
controls a current I
CONT
to keep the voltage Vo of the node between the resistors R
1
a
and R
2
a
at a given constant level.
The power supply voltage V
DD
is equal to, for example, 85 V, and the bias setting voltage Vo is equal to, for example, 30 V. By controlling the current flowing in the resistor R
1
a
, it is possible to maintain the bias setting voltage Vo at the constant level. That is, the following equations stand:
Vo=V
DD
−Io Ra
1
Io=I
CONT
+I
APD
Thus, even if the optical input power changes and the current I
APD
is thus changed, the bias setting voltage Vo can be controlled at the constant level by controlling the current I
CONT
to maintain the current Io at a constant level.
The bias voltage V
APD
and the current I
APD
applied to the APD
101
are obtained as solutions of the following simultaneous equations:
I
APD
=(
e?&lgr;/h c
)&eegr;
M
Pin  (1)
V
APD
=(
Vo−Vin
)−
R
2
a I
APD
  (2)
M
=1/[1−(
V
APD
/V
B
)
n
]  (3)
where e is the charge of electrons, &lgr; is the wavelength of the optical input, h is Planck's constant, c is the speed of light, &eegr; is the quantum efficiency, M is the multiplication factor, Pin is the average optical input power, V
APD
is the bias voltage of the APD, Vo is the bias setting voltage, I
APD
is the optical current of the APD, V
B
is the breakdown voltage of the APD, and n is a value (fitting coefficient) determined by the physical properties of the APD.
As the optical input power Pin increases, the current I
APD
flowing in the APD
101
is increased, and the voltage drop developing across the resistor R
2
a
is increased. Thus, the bias voltage V
APD
is decreased and the multiplication factor M is also decreased. In contrast, as the optical input power Pin decreases, the current I
APD
flowing in the APD
101
is decreased, and the voltage drop developing across the resistor R
2
a
is reduced. Thus, the bias voltage V
APD
is increased and the multiplication factor M is also increased.
FIG. 3
is a graph of a multiplication factor vs. optical input level characteristic. In order to widen the dynamic range of the optical receiver, the multiplication factor M is set as high as, for example, about 10-20 at the minimum optical input level, and is set as low as, for example, about 1-3 at the maximum optical input level. The tolerable variation range of the optical input power Pin defines the dynamic range of the optical receiver.
In order to stabilize the APD bias circuit shown in
FIG. 2
in a situation in which the optical input power varies, it is proposed, as shown in
FIG. 4
, to provide a capacitor C
2
a
between the ground and a node connecting the resistor R
2
a
and the APD
101
together. Let &tgr;
0
, &tgr;
1
and &tgr;
2
be respectively the time constants of the bias control circuit
110
, the bias setting voltage Vo, and the circuit made up of the resistor R
2
a
and the capacitor C
2
a
, the time constant &tgr;
1
being inversely proportional to the time constant &tgr;
2
.
In this case, it is necessary to determine the time constants &tgr;
1
and &tgr;
2
so that the following conditions (a) and (b) are satisfied. The condition (a) requires that, when the optical input is broken or cut off from the maximum receive level, the bias voltage V
APD
does not exceed the breakdown voltage V
B
. The condition (b) requires that, when the optical input rises to the maximum receive level from the input broken level, or when an optical surge is input, the APD current I
APD
does not exceed the maximum rated currents of the APD and the equalizer amplifier.
FIGS. 5A
,
5
B and
5
C are graphs related to a case where the optical input is broken from the maximum receive level. More particularly,
FIG. 5A
shows a variation in the optical input power,
FIG. 5B
is a variation in the bias voltage, and
FIG. 5C
is a variation in the APD current. As shown in
FIG. 5A
, if the optical input power decreases to the optical input broken level from the maximum receive level for a short time of a few microseconds to hundreds of microsecond due to a failure in the optical transmission line or an abnormality at the transmission side, the current I
APD
flowing in the APD
101
decreases in accordance with the optical input power. Thus, as shown in
FIG. 5B
, the bias setting voltage Vo increases based on the time constant &tgr;
0
. Generally, the time constant &tgr;
0
is a value which does not allow the bias control circuit
110
to follow the variation in the optical input power. Hence, the bias voltage V
APD
indicated by the broken line increases and may exceed the breakdown voltage V
B
.
As shown in
FIG. 5C
, the APD current I
APD
decreases as the optical receive level decreases. However, a breakdown current flows due to a critical situation in which the bias voltage V
APD
increases and exceeds the breakdown voltage V
B
.
FIGS. 6A
,
6
B and
6
C are related to a case where the optical input increases to the maximum optical receive level from the input broken level. More particularly,
FIG. 6A
shows a variation in the optical input power,
FIG. 6B
shows a variation in the bias voltage, and
FIG. 6C
shows a variation in the APD current. As shown in
FIG. 6A
, if the optical input increases to the maximum receive level from the optical input broken level for a short time of a few microseconds to hundreds of microsecond, the bias setting voltage Vo is maintained at a given level as indicated by the solid line in FIG.
6
B. Correspondingly, the bias voltage V
APD
remains at the previous level, or gradually decreases.
Thus, as shown in
FIG. 6C
, the APD current I
APD
increases over the absolute maximum rated current because the optical input power increases due to the multiplication factor M still being large. This causes degradation of the APD
101
and

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