Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2000-01-03
2004-06-22
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C438S048000, C438S072000, C438S636000
Reexamination Certificate
active
06753584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the present invention relates to an anti-reflective enhancement for integrated circuit fabrication. In particular, the present invention relates to an anti-reflective enhancement for reducing critical dimension loss during mask patterning. More particularly, the present invention relates to formation of a metal silicon nitride antireflective coating layer that resist “foot poisoning” of a masking layer and its detrimental effects.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the microelectronics industry, the process of miniaturization entails shrinking the size of individual semiconductor devices and crowding more semiconductor devices within a given unit area. With miniaturization, problems arise such as proper electrical isolation between components. Attempts to isolate components from each other in the prior art arm constrained by photolithographic limits of about 0.25 microns. One way to form structures that electrically isolate conductive materials on a semiconductor substrate from each other is to use photolithography in patterning dielectrics layers upon the semiconductor substrate.
To form a metallization wiring layer on a semiconductor substrate by photolithography, a photoresist mask is used to pattern the metallization wiring layer. The mask has directed therethrough a beam of light, such as ultraviolet (UV) light and deep UV (DUV) light (~250 nm), to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match, respectively, openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the semiconductor substrate on which the photoresist coating is located. Light is directed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the size of the photolithographic coating and that develops the portions of the photoresist coating that are unasked and are intended to remain. The undeveloped portions are thereafter remove. Other photolithographic techniques for formation of device features are also possible.
As dimensions shrink below about 0.25 microns, the prior art technique of forming metallization wiring layers becomes more difficult to achieve. Light that is reflected during exposure of a photoresist tends to blur the boundary between two metallization lines and the space therebetween. This blur can cause wider metallization lines than designed, which excessive width will either bridge and short out the circuit or will cause unwanted “cross talk” such that the device is rendered defective.
In general, the blurred edge of a critically dimensioned photoresist layer caused by reflected light in photolithographic techniques also result in problems in contact corridors, vias, wiring trenches, and isolation trenches, where the dimensions are patterned below about 0.25 microns. For example, a contact corridor that is too wide will cause notching into a gate stack during a contact corridor etch. Notching causes encroachment into conductive areas of an adjacent gate stack and filling the contact corridor with metallization material can cause a short to occur between the contact and the conductive elements of the adjacent gate stack. A wiring trench that is too wide will cause “cross talk” with the wiring in a neighboring trench so as so to compromise and accuracy of the integrated circuit associated therewith.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template is currently limited in commercial applications to widths of about 0.25 microns. In turn, the dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming semiconductor device features that have a size that is reduced from what can be formed with conventional photolithography.
During photolithography, reflected light that occurs during exposure of a mask tends to blur the desired image because the reflected light escapes beyond exposed regions on the photoresist. The blurring problem is caused by reflected light affecting areas of the photoresist that are outside the design pattern.
FIG. 1
illustrates the problem of blurring caused by reflected light that occurs during exposure of a photoresist. A semiconductor structure
10
may be, for example, a semiconductor substrate
12
that was designed to have a width D, but due to blurring caused by reflectivity of patterning light from structures beneath the photoresist, semiconductor substrate
12
has an actual width A. The variance between design width D and actual width A is illustrated as the distance 2(B/2) or B. By way of example, semiconductor substrate
12
was designed to have a width D of 10 in arbitrary units, but due to blurring caused from reflectivity, the actual width A is nine in arbitrary units. It can be seen that a ten percent variance between design and actual width has occurred.
As miniaturization technology continues, a blurring variance of B as illustrated in
FIG. 1
will increase relative to an ever-decreasing design width D. Thus, as also illustrated in
FIG. 1
, a miniaturized semiconductor substrate
12
′ that may have a design width D′ of to two and one-half in arbitrary units but with the variance of B, will have the effect of causing a 40 percent error. A variance of B may leave insufficient space upon miniaturized semiconductor substrate
12
′ to form desired contacts or structures. It can be seen from the demonstration illustrated in
FIG. 1
that the need to eliminate or substantially reduce blurring must keep pace with miniaturization.
Another hindrance to photolithographic limitations are conventional antireflective coating (ARC) schemes. Prior art methods for avoiding reflected light and its photoresist blurring problems include using layers such as titanium nitride or organic materials that reduce the reflected light in order to better control resolution of the photoresist. As the ever-increasing pressure to miniaturize bears upon the microelectronics industry, the conventional antireflective enhancements such as a titanium nitride layer, organic layers, or other layers known in the art are proving inadequate at resolutions below about 0.25 microns.
One problem at a dimension below about 0.25 microns is that of fouling caused by titanium nitride or organic materials. Fouling is defined as a tendency for a selected antireflective layer to resist staying within preferred boundaries. Resistance to staying within preferred boundaries tends to cause photolithographic techniques to be compromised.
When the ARC is a polymer film, it is applied directly to the semiconductor stru
Louie Wai-Sing
Pham Long
Workman Nydegger
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