Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2002-11-19
2004-11-09
Tran, Minhloan (Department: 2826)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S128000, C438S600000, C438S601000, C438S630000, C257S530000, C257S528000, C257S050000, C257S209000, C257S752000, C257S754000
Reexamination Certificate
active
06815264
ABSTRACT:
TECHNICAL FIELD
The invention relates to antifuses, and methods of producing antifuses.
BACKGROUND
Antifuses are useful devices, which may be used in circuits to program data or to trim/correct the circuit to remove unwanted offsets. A common antifuse component is a parallel plate capacitor which is insulating before fusing and conducting after. These components may need to be large due to the area of the capacitor used as a fuse. Extra processing steps may be required to fabricate the capacitor which are not otherwise needed to make the other circuit components. This increases cost and complexity. It is better to reuse layers on an existing process sequence to manufacture the fuses.
The insulating material may be an oxide or undoped polysilicon layer (see U.S. Pat. No. 5,844,297: Antifuse device for use on a field programmable interconnect chip. Crafts et al.) when making a vertical antifuse structure.
In the past a conventional fusing element was used on chip, by making a very narrow piece of metal or polysilicon conductor which is melted or vaporised by a high electric current. The action of fusing causes the passivation layers, which protect the chip from moisture, to be compromised. Also the fuse residue tends to be distributed over the surface of the chip. Very high current levels are needed to melt and vaporise the fuse material. The method is unsatisfactory for integrated circuit use.
Another possibility is to use a junction diode in the single crystal silicon substrate (see U.S. Pat. No. 5,847,441: Semiconductor junction antifuse circuit. D J. Cutter, K D. Beigel, Micron Technology, Inc.). The diode may be ‘blown’ by applying a large reverse current, so that it becomes a short circuit. A drawback of this method is the need to isolate the fuse junctions from the conducting substrate by placing the device in a well of opposite doping type to substrate. Another disadvantage is the high current required to cause doping redistribution in the fuse; the silicon is a good conductor of heat and diffusion is slow in a single crystal.
Dopant diffusion is fast for polysilicon due to movement through the grain boundaries. Thus the currents required to fail a polysilicon antifuse are much lower than a single crystal device.
SUMMARY
According to the invention there is provided an antifuse and a method of producing antifuses, as set out in the accompanying claims.
REFERENCES:
patent: 5311039 (1994-05-01), Kimura et al.
patent: 5844297 (1998-12-01), Crafts et al.
patent: 5847441 (1998-12-01), Cutter et al.
patent: 5905670 (1999-05-01), Babson et al.
patent: 6258700 (2001-07-01), Bohr et al.
patent: WO 01/69658 (2001-06-01), None
Daniels Ian G
Ellis John N
Stribley Paul Ronald
Forde Remmon R.
Thompson Hine LLP
Tran Minhloan
Zarlink Semiconductor Limited
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