Antifuse with double via, spacer-defined contact

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257 50, 257 52, H01L 2904, H01L 2900

Patent

active

056635915

ABSTRACT:
The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate. The method comprises forming a first metal interconnection layer on the first insulating layer; forming a relatively thin, second insulating layer over the first metal interconnection layer with a via where the antifuse is to be located to expose the first metal interconnection layer; forming first spacer regions on the sidewalls of the second insulating layer; forming a programming layer on the second insulating layer and in the via to contact the first metal interconnection line; forming second spacer regions on the sidewalls of the programming layer in the via; forming a barrier metal layer on the programming layer; forming a relatively thick, third insulating layer on the barrier metal layer with a second aperture to expose a portion of the barrier metal layer; and forming a second metal interconnection layer on the third insulating layer and in the second aperture to contact the portion of the second barrier metal layer. The spacer regions force programming to occur away from the sidewalls of the via for greater uniformity of programming voltages and greater stability on the R.sub.ON resistance. Additionally, the capacitance of the unprogrammed antifuse is reduced.

REFERENCES:
patent: 3675090 (1972-07-01), Neale
patent: 4217374 (1980-08-01), Ovshinsky et al.
patent: 4226898 (1980-10-01), Ovshinsky et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4748490 (1988-05-01), Hollingsworth
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5100827 (1992-03-01), Lytle
patent: 5106773 (1992-04-01), Chen et al.
patent: 5120679 (1992-06-01), Boardman et al.
patent: 5166556 (1992-11-01), Hsu et al.
patent: 5181096 (1993-01-01), Forouhi
patent: 5191241 (1993-03-01), McCollum et al.
patent: 5196724 (1993-03-01), Gordon et al.
patent: 5210598 (1993-05-01), Nakazaki et al.
patent: 5233217 (1993-08-01), Dixit et al.
patent: 5248632 (1993-09-01), Tung et al.
patent: 5250464 (1993-10-01), Wong et al.
patent: 5272101 (1993-12-01), Forouhi et al.
patent: 5284788 (1994-02-01), Spratt et al.
patent: 5290734 (1994-03-01), Boardman et al.
patent: 5322812 (1994-06-01), Dixit et al.
patent: 5328865 (1994-07-01), Boardman et al.
patent: 5329153 (1994-07-01), Dixit
patent: 5362676 (1994-11-01), Gordon et al.
patent: 5369054 (1994-11-01), Yen et al.
patent: 5373169 (1994-12-01), McCollum et al.
patent: 5374832 (1994-12-01), Tung et al.
patent: 5381035 (1995-01-01), Chen et al.
patent: 5384481 (1995-01-01), Holzworth et al.
patent: 5387812 (1995-02-01), Forouhi et al.
patent: 5404029 (1995-04-01), Husher et al.
patent: 5411917 (1995-05-01), Forouhi et al.
patent: 5440167 (1995-08-01), Iranmanesh
patent: 5451810 (1995-09-01), Tigelaar et al.
G. H. Chapman, et al., "A Laser Linking Process for Restructurable VLSI", CLEO '82 (Apr. 1982), pp. 1-5.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Antifuse with double via, spacer-defined contact does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Antifuse with double via, spacer-defined contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Antifuse with double via, spacer-defined contact will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-311583

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.