Antifuse with double via contact and method of manufacture there

Details Antifuse with double via contact and method of manufacture there Antifuse with double via contact and method of manufacture there

1994-02-23

1995-08-08

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257 30, 437 51, 437190, 437192, 437922, H01L 2702, H01L 4500, H01L 2144, H01L 2148

Patent

active

054401674

ABSTRACT:
The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate. The method comprises forming a first metal interconnection layer on the first insulating layer; forming a programming layer on the first metal interconnection line; forming a relatively thin, second insulating layer over the programming layer; forming a first aperture through the second insulating layer where the antifuse is to be located to expose a portion of the programming layer; forming a barrier metal layer on the second insulating layer and in said first aperture to contact the portion of said programming layer; forming a relatively thick, third insulating layer on the barrier metal layer; forming a second aperture to expose a portion of the barrier metal layer; and forming a second metal interconnection layer on the third insulating layer and in the second aperture to contact the portion of the second barrier metal layer.

REFERENCES:
patent: 4217374 (1980-08-01), Ovshinsky et al.
patent: 4226898 (1980-10-01), Ovshinsky et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 5100827 (1992-03-01), Lytle
patent: 5284788 (1994-02-01), Spratt et al.
G. H. Chapman et al., "A Laser Linking Process for Restructurable VLSI", CLEO '82 (Apr. 1982) 5 pages.

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