Antifuse memory cell and antifuse memory cell array

Details Antifuse memory cell and antifuse memory cell array Antifuse memory cell and antifuse memory cell array

2002-08-28

2004-04-13

Mai, Son (Department: 2818)

Static information storage and retrieval

Read only systems

Fusible

C365S225700, C327S525000

Reexamination Certificate

active

06721197

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory cells. More particularly, the present invention relates to an integrated circuit memory cell structure that employs antifuses to implement an antifuse memory cell (AMC) and an array of AMCs.
2. The Background Art
There are a variety of programmable integrated circuit memory cells and arrays of these programmable integrated circuit memory cells known to those of ordinary skill in the art. Different memory types include dynamic random access memory (DRAM), static random access memory (SRAM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and Flash memory. Each of these known memory cell technologies have at least one of the following advantageous characteristics: non-volatility; high density; low power; one transistor per cell; in-system rewritability; full bit alterability; and a high performance read.
In field programmable gate array (FPGA), the logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. In a reprogrammable FPGA, the programmable elements are typically passgates controlled by information stored in a configuration memory that is often implemented by SRAM or in some implementations by Flash memory. In a one time programmable FPGA, the programmable elements are typically antifuses that represent an open state until programmed. Both antifuse based programmable architectures and SRAM based reprogrammable architectures are well known in the FPGA art.
The programming of SRAM and Flash based configuration memories in an FPGA can be performed in parallel. In contrast, the programming of an antifuse based FPGA is performed in a serial manner. As a result, the programming time for an antifuse based FPGA can be longer than the programming time for an SRAM or Flash based FPGA. Further, current sneak paths which occur during the programming of an antifuse based FPGA because there is typically no isolation between the antifuses in an antifuse based FPGA do not occur when SRAM or Flash based configuration memories are employed.
In comparison to an antifuse based FPGA, one important drawback to an SRAM based FPGA is the significant integrated circuit area required by each SRAM cell. Although a Flash based configuration memory does not require as much integrated circuit area as an SRAM based configuration memory, a Flash based configuration memory requires a custom integrated circuit process that is both expensive to implement and to test rather that a standard CMOS process.
In
FIG. 1
, a PROM that includes N-channel MOS transistors
2
, bitlines
4
, and employs antifuses
6
as the programmable elements in the memory is illustrated. In the PROM, the antifuses
6
in a row can be programmed by turning on the N-channel MOS transistors
2
in the row and simultaneously applying a programming voltage to the bitline
4
of the corresponding antifuse
6
that is being programmed. The PROM is employed as a memory device by turning on the N-channel MOS transistors
2
in a row and reading out on a bitline
4
through a sensing device whether the corresponding antifuse
6
has been programmed.
Unlike SRAM or Flash, the PROM of
FIG. 1
is not suitable to be employed as a configuration memory for an FPGA because the PROM does not store a static voltage like the flip-flop of an SRAM memory cell or the floating gate of a Flash memory cell.
BRIEF DESCRIPTION OF THE INVENTION
According to the present invention, an antifuse memory cell includes an n-channel MOS transistor and first and second antifuses. A common node is formed by first electrodes of antifuses and the drain of the n-channel MOS transistor. Second electrodes of antifuses are connected to programming and bias circuitry. The contents of the memory cell are determined by programming either the first or second antifuse. To program either antifuse, Vpp is applied to the second electrode of the antifuse that is being programmed, Vpp/2 is applied to the second electrode of the antifuse that is not being programmed, and the common node is placed at ground potential.
According to another aspect of the present invention, when the antifuses have lower electrodes that are formed in the substrate, the required programming current can also be provided by a minimally sized n-channel MOS transistor.
According to another aspect of the present invention, the antifuse memory cells according to the present present invention may be formed in an array.


REFERENCES:
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5148391 (1992-09-01), Zagar
patent: 5194759 (1993-03-01), El-Ayat et al.
patent: 5272101 (1993-12-01), Forouhi et al.
patent: 5299152 (1994-03-01), Ishihara et al.
patent: 5327024 (1994-07-01), Cox
patent: 6333666 (2001-12-01), Kim et al.

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