Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2005-06-28
2009-06-30
Garber, Charles D. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S281000, C438S762000, C438S770000, C438S981000, C257SE21625, C257SE29133
Reexamination Certificate
active
07553704
ABSTRACT:
An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
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Baird Robert W.
Lee Gordon P.
Min Won Gi
Zuo Jiang-Kai
Freescale Semiconductor Inc.
Garber Charles D.
Ingrassia Fisher & Lorenz P.C.
Pompey Ron E
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