Antifuse circuit being programmable by using no connection pin

Details Antifuse circuit being programmable by using no connection pin Antifuse circuit being programmable by using no connection pin

2000-12-18

2001-12-25

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

C327S526000

Reexamination Certificate

active

06333666

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an antifuse circuit; particularly to an antifuse circuit for providing an external high voltage to an antifuse programming circuit through the use of a no connection (NC) pin which is not used in the chip operation, and reducing the number of transistors which constitute a detection and latch unit to thereby improve the stabilization of high voltage signals and the integration of memory devices.
DESCRIPTION OF THE PRIOR ART
Referring to
FIG. 1
, there is described a block diagram of a conventional antifuse circuit.
In
FIG. 1
, an oscillator
10
generates a first clock signal CLK and a second clock signal CLKB based on a programming signal PGM coupled thereto. Then, the first and the second clock signals CLK and CLKB are fed to a high voltage generator
20
.
The high voltage generator
20
produces a high voltage HV by using the first and the second clock signals CLK and CLKB inputted thereto and provides the high voltage HV to an antifuse programming circuit
30
which programs an antifuse element through the use of the high voltage HV.
A power-up detecting circuit
40
generates a power stabilization signal PWRUP by sensing a supply voltage Vcc.
A power-up pulse circuit
50
generates a first to a third control signal PWR, PWRB and PWR_P by using the power stabilization signal PWRUP fed thereto and supplies the control signals to the antifuse programming circuit
30
, wherein the control signals are used to detect whether the antifuse element is programmed or not, and to latch the result of the detection.
The antifuse programming circuit
30
programs the antifuse element, or detects whether the antifuse element is programmed or not and latches the result of the detection by using the first to third control signals PWR, PWRB and PWR_P, the high voltage HV and a precharge signal PC coupled thereto, to thereby produce an output Rout.
Referring to
FIG. 2
, there is illustrated a schematic diagram of the conventional antifuse programming circuit
30
.
When programming an antifuse element F
1
, a voltage higher than 8V is supplied to the high voltage node HV, and the precharge signal PC and a select node SA become a logic high state. Thereafter, the antifuse element F
1
is programmed by the voltage difference between its both ends.
In case the antifuse element F
1
is unprogrammed, a leak voltage close to OV is fed to a first node A
1
. Then, a third PMOS transistor P
3
is turned on by the second control signal PWRB and a fourth PMOS transistor P
4
is turned on by the leak voltage provided through the first node A
1
. As a result, a supply voltage is coupled to a second node A
2
. The supply voltage fed to the second node A
2
turns on a fifth NMOS transistor N
5
that in turn connects an input node A
3
of a latch unit
303
to ground. The latch unit
303
outputs an unprogrammed signal having a logic high state by the ground voltage coupled to its input node A
3
.
On the other hand, in case the antifuse element F
1
is programmed, a voltage Vcc-Vt is inputted to the first node A
1
so that the fourth PMOS transistor P
4
is turned off and the fourth NMOS transistor N
4
is turned on by the third control signal PWR_P. Thereafter, the second node A
2
becomes to have a logic low state. Then, the fifth PMOS transistor P
5
is turned on by the second control signal PWRB and the sixth PMOS transistor P
6
is turned on by the logic low level of the second node A
2
. As a result, the supply voltage is provided to the third node A
3
and the latch unit
303
outputs a programmed signal having a logic low state by the supply voltage on the third node A
3
.
As can be seen above, the high voltage used in programming the antifuse element is provided from the antifuse programming circuit by using the oscillator and the high voltage generator embodied in a chip. However, an unstable voltage has been provided to the antifuse programming circuit by the variance of the high voltage due to the fabrication variance and the temperature when fabricating the oscillator and the high voltage generator. As a result, the failure rate increases and the integration decreases since the oscillator and the high voltage generator occupy a large area.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a circuit for providing an antifuse programming circuit with an external high voltage delivered by using a no connection (NC) pin that is not used in the chip operation.
In accordance with an embodiment of the present invention, there is provided a antifuse circuit comprising: a power-up detecting circuit for generating a power stabilization signal by detecting a supply voltage; a power-up pulse circuit for generating a first and a second control signal in response to the power stabilization signal; an antifuse programming circuit for, under the control of the first and the second control signals, detecting whether an antifuse element is programmed or not, latching the result of the detection and programming the antifuse element in response to an external high voltage and a precharge signal; a pin for receiving the external high voltage so as to program the antifuse element; a pad for providing the external high voltage to the inside of the chip; and a diode for supplying the external high voltage to the antifuse programming circuit and preventing a voltage of the antifuse programming circuit from being provided to the pin.


REFERENCES:
patent: 4730129 (1988-03-01), Kunitoki et al.
patent: 5600277 (1997-02-01), Koelling
patent: 5619469 (1997-04-01), Joo
patent: 5789970 (1998-08-01), Denham
patent: 6087890 (2000-07-01), Kim
patent: 6157583 (2000-12-01), Starnes et al.
patent: 6281739 (2000-08-01), Matsui

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