Antifuse circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit

Reexamination Certificate

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Reexamination Certificate

active

06741117

ABSTRACT:

TECHNICAL FIELD
An antifuse circuit for use in a semiconductor memory device is disclosed which can be used as a replacement for a defective memory cell thereby making the cell operable in a more stable manner.
DESCRIPTION OF RELATED ART
Advances in semiconductor fabrication techniques and in a memory design have led to the commercial production of semiconductor memories, which hold millions of bits of information. It is important that a manufacturer verify that each and every bit or memory cell on a semiconductor memory chip is addressable before the chip is sold.
However, due to the large number of bits or memory cells on each chip, it is unrealistic to assume that chips can be fabricated with every bit or memory cell position functioning. Physical defects in the manufacturing process tend to make it very difficult to manufacture devices of such a high bit density without one or more bits or memory cells becoming defective.
Although a manufacturer cannot sell a semiconductor memory chip without ensuring that the full range of addresses is functional, discarding memory chips having defective bits is wasteful, inefficient and costly. Thus, it is desirable to provide an approach, which allows fabrication of a memory chip with redundant bits or cells to compensate for the inevitable bit or memory cell defects.
Designers have incorporated one or more redundant rows or columns into memory devices to provide a method of patching bit or memory cell errors in memory chips. That is, redundant cells are provided which can be accessed when testing indicates the existence of bit or memory cell defects in the memory device. If, for example, a bit or a memory cell in a first column of a memory array is found to be defective, the entire first column is typically replaced by using a substitute column. The patch or replacement is accomplished using a bank of polysilicon fuses. The address of the patched or replaced column is burned into the fuse bank using techniques known in the art. Thus, whenever the address of the defective column is presented to the semiconductor memory, the replacement column will be accessed instead. This solution reduces the number of wasted memory chips, which would otherwise be unusable due to defective bits or memory cells.
However, the above procedure of patching the defected semiconductor memory cell needs to be performed before packaging the memory device. After packaging, the fuse could not be broken or blown out by using a laser beam of a conventional technique. That is, using such a conventional fuse bank, it could not repair the defected semiconductor device after packaging the semiconductor memory device. Therefore, in order to overcome the above problem after packing, an antifuse circuit is further introduced in a semiconductor memory device.
FIG. 1
is a schematic block diagram illustrating a conventional antifuse circuit employing an antifuse.
As shown, the conventional antifuse circuit includes an antifuse block
10
, a power-up signal generator
20
, a high-voltage generator
30
and a redundancy circuit
40
.
The antifuse circuit
10
receives a program-mode selection signal PGM and an address signal ADDR to generate an antifuse enable signal ANT_EN. The power-up signal generator
20
outputs a power-up signal VEXT_DET representing a stabilization of a power provided in the semiconductor device after the power is supplied to the semiconductor device. The high-voltage generator
30
supplies a high-voltage to the antifuse block
10
in order to program the antifuse block
10
. The redundancy circuit
40
servers to perform the replacement operation for a defective memory cell in response to the antifuse enable signal ANTI_EN from the antifuse block
10
.
FIG. 2
is a circuit diagram of the conventional antifuse block
10
shown in FIG.
1
.
As shown, the antifuse block
10
includes an antifuse unit
11
for controlling the antifuse being short-circuited or insulated in response to the program mode selection signal PGM and the address signal ADDR. The antifuse block
10
also includes an antifuse precharge unit
12
for precharging the antifuse unit
11
according to a power-up signal.
The antifuse unit
11
includes a NAND gate ND
1
, a PMOS transistor MP
1
, two NMOS transistors MN
1
and MN
2
, an antifuse ANT_FUSE and two invertors I
1
and I
2
.
The output port of the NAND gate ND
1
is connected to a gate of the PMOS transistor MP
1
and a gate of NMOS transistor MN
2
and receives two signals PGM and ADDR. The PMOS transistor MP
1
is coupled to an external voltage source of a first voltage level Vext between the NMOS transistor MN
2
. The NMOS transistor MN
2
is coupled to another NMOS transistor MN
1
in serial. A gate of the MN
1
is coupled to the PGM and the NMOS transistor MN
1
is coupled to a ground of a second voltage level Vss. The antifuse ANTI_FUSE is coupled to a common node N
1
of the MP
1
and MN
2
. The antifuse ANTI_FUSE receives a high voltage signal VBB_ANTI generated from the high-voltage generator
30
. The invertors I
1
and I
2
are coupled to the common node N
1
in order to generate the antifuse enable signal ANTI_EN. The invertors I
1
and I
2
employ an internal voltage source of a third voltage level Vint as an operation voltage and output the antifuse enable signal ANTI_EN corresponding a fourth voltage level of the node N
1
to the redundancy circuit
40
by latching the fourth voltage level of the node N
1
.
The antifuse precharge unit
12
includes an inverter
13
and a PMOS transistor MP
2
. The inverter
13
serves to invert the power-up signal VEXT_DET. The PMOS transistor MP
2
receives an inverted power-up signal from the inverter
13
to thereby selectively couple the first voltage level Vext to the node N
1
.
FIG. 3
is a timing diagram for explaining an operation of the antifuse block shown in FIG.
2
.
Hereinafter, a conventional antifuse circuit by employing the antifuse is explained in detail as referring to the
FIGS. 1
to
3
.
The high-voltage generator
30
outputs a voltage signal of a fifth voltage level VBB_ANTI. The fifth voltage level VBB_ANTI can vary according to the operational mode. It becomes a low-voltage level (less than, e.g., −3V) in a program mode and becomes, e.g., 0V as like as a ground voltage level Vss in a normal mode.
In the program mode, when the PGM of a high voltage level and the ADDR of a high voltage level are inputted to the antifuse unit
11
, the ND
1
's output becomes a low voltage level. The MP
1
becomes turned on and MN
2
becomes turned off. Therefore, the fourth voltage level of the node N
1
is increased to the first voltage level Vext, e.g., +3.3V and the fifth voltage level VBB_ABTI of, e.g., −3V is applied to another terminal of the antifuse ANTI_FUSE. As a result, an insulation material or layer of the antifuse becomes broken and the antifuse ANTI_FUSE is then short-circuited as demonstrated in a “short circuit state” A
1
of FIG.
3
.
On the other hand, in the program mode, if the PGM is inputted as a high voltage level signal and the ADDR is inputted as a low voltage level signal, then an output of the ND
1
becomes a high voltage level. Therefore, the NMOS transistors MN
1
and MN
2
become turned on and the node N
1
become a low voltage level. As a result, a voltage between 0V and −3V is applied both ends of the antifuse ANTI_FUSE and the insulation material or layer of the antifuse is unbroken to thereby maintain the initial insulation as depicted in an “insulation state A
2
” of
FIG. 3
When the antifuse ANTI_FUSE is programmed as the short circuit A
1
of
FIG. 3
, at the initial state, an external voltage source of the first voltage level Vext is applied to a semiconductor and a power-up signal VEXT_DET is inputted to the antifuse precharge unit
12
. The voltage level of the power-up signal VEXT_DET is increased according to the first voltage level Vext and it becomes a low voltage level when the first voltage level Vext becomes stable.
On the other hand, the program mode selection signal PGM is a low voltage level and

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