Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1997-05-15
2002-09-10
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S050000, C257S051000
Reexamination Certificate
active
06448627
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the general area of programmable logic and memory, more particularly to antifuses for use in those technologies.
(2) Description of the Prior Art
In recent years the popularity of field programmable logic and write-once memories has grown significantly. These systems are generally based on antifuses. The latter are connections between wires that are initially open circuits but which can, through suitable external means, be selectively (and irreversibly) converted to short circuits.
One of the ways to activate an antifuse is by applying a suitable voltage (generally less than about 20 volts) across it. This causes the antifuse to change from its insulating to its conducting state in a few microseconds. For a typical antifuse of the current art, having an area of about one square micron, the resistance in the open state will be about 10
9
ohms while the resistance in the conducting state will be about 500 ohms.
Many antifuse systems are based on amorphous silicon, which has high resistivity, but which, after heating, recrystallizes and drops its resistivity substantially. An example of this type of antifuse is given by Roesner (U.S. Pat. No. 4,796,074 January 1989). Other types of material mentioned by Roesner include germanium, carbon and tin and all depend on a change in grain size from amorphous, or very small crystallites, to relatively large grains. An additional drop in resistivity is achieved by the activation of interstitial dopant atoms (such as might be introduced through ion implantation). Thus Roesner teaches that the maximum temperature to which antifuse material may be exposed during processing must be less than about 600° C.
A number of improvements in the details of how to manufacture antifuses of the amorphous silicon type have been described by Dixit (U.S. Pat. No. 5,322,812 June 1994). Of particular importance is the maintenance of a high level of cleanliness. The maximum processing temperature is kept to about 540° C. and great care is taken to avoid the presence of nitrogen since small amounts of silicon nitride were found to degrade the performance of the antifuses.
An alternative antifuse system to the amorphous semiconductor variety discussed above is one that is based on oxide-nitride-oxide (ONO). ONO comprises a structure of three layers—silicon oxide, silicon nitride, and silicon oxide. When such a structure is subjected to a suitable applied voltage its resistance changes from about 10
9
ohms to about 500 ohms by blowing up the ONO dielectric.
An example of an antifuse based on the ONO system is shown in FIG.
1
. The ONO system has been discussed by, for example, S. Chiang et al. in the 1992 Symposium on VLSI Technology Digest pp. 20-21. Layer
2
of heavily doped N type silicon is in contact with silicon substrate
1
. Layer
3
comprises thermal silicon oxide, typically about 38 Angstroms thick. Layer
4
comprises silicon nitride, typically about 75 Angstroms thick, while layer
5
comprises silicon oxide, typically about 28 Angstroms thick. Layer
6
is a ‘cap’ for the antifuse comprising a layer of heavily doped N type silicon about 4,000 Angstroms thick. Layer
6
will also serve as an electrical connector to other parts of the integrated circuit (IC) of which it is a part. Layer
7
comprises field oxide, about 1,300 Angstroms thick, whose purpose is to isolate the antifuse from other parts of the IC.
Layer
8
in
FIG. 1
comprises silicon nitride and is used as a mask during processing to define the area of the antifuse. Its thickness is generally about 400 Angstroms.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide an antifuse structure that has improved characteristics relative to similar antifuse structures known to the prior art.
Another object of the present invention has been to provide an antifuse structure that has lower cost and higher speed than similar antifuse structures known to the prior art.
Yet another object of the present invention has been to provide a method for manufacturing said antifuse structure.
These objects have been achieved in a structure comprising a region of heavily doped N type silicon coated with a layer of ONO (oxide-nitride-oxide). Top contact to the ONO is made through a layer of tungsten silicide sandwiched between two layers of N type polysilicon. A cost effective method for manufacturing said antifuse structure is described.
REFERENCES:
patent: 4796074 (1989-01-01), Roesner
patent: 5126290 (1992-06-01), Lowrey et al.
patent: 5303199 (1994-04-01), Ishihara et al.
patent: 5322812 (1994-06-01), Dixit et al.
patent: 5412244 (1995-05-01), Hamdy et al.
patent: 5572061 (1996-11-01), Chen et al.
patent: 5619063 (1997-04-01), Chen et al.
Chartered Semiconductor Manufacturing Ltd.
Eckert II George C.
Pike Rosemary L. S.
Saile George O.
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