Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-06-29
2001-04-17
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S050000, C257S565000
Reexamination Certificate
active
06218722
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to programmable antifuses and to methods of making the same.
BACKGROUND OF THE INVENTION
Antifuses have been known for some time and are disclosed for example in U.S. Pat. Nos. 3,191,151; 3,742,592; 5,019,878; and 5,298,784. Antifuses are devices which have a high impedance before programming and a low impedance after programming, and are used widely in integrated circuit structures. An antifuse is the converse of a fuse, which can be employed in a similar manner. Use of an antifuse permits the tuning of various analog circuit parameters, the programming of digital logic, and the selection of certain pieces of redundant circuitry. An exemplary application for antifuses (given by way of example only) is to switch desired resistances into a voltage controlled oscillator (VCO), so that the center frequency and range of the VCO will be within desired specifications.
Antifuses can be formed from transistor or diode structures which normally have a high impedance when reverse biased. The appropriate PN junction of the device can be shorted by applying a large reverse bias, causing part of the junction to melt and causing the metal which contacts the junction to flow into the molten region, thereby creating a low impedance metal filament.
Conventional antifuse structures typically require a relatively high programming voltage and energy, which may cause damage to the remainder of the integrated circuit in which the antifuse is located. It is therefore an object of the invention to provide an improved antifuse structure, and a method of forming an antifuse, which require a lower programming voltage and energy than have typically been the case in the past.
BRIEF SUMMARY OF THE INVENTION
Accordingly, in one of its aspects the invention provides a method of making an antifuse in a silicided single polysilicon bipolar transistor, said transistor comprising:
(i) a collector layer,
(ii) a base layer overlying said collector layer and having an upper surface,
(iii) an emitter structure overlying said base layer, said emitter structure projecting above said base layer and having a sidewall extending above said base layer, said emitter structure also having an upper surface,
(iv) a first conductive silicide layer on said upper surface of said base layer, and the second conductive silicide layer on said upper surface of said emitter structure, said first and second conductive silicide layers not contacting each other,
said method comprising providing a narrow oxide spacer ring surrounding said sidewall of said emitter structure, said spacer ring being formed by chemical vapor deposition and anisotropic plasma etching, said first conductive silicide layer surrounding said spacer ring, said method further comprising applying a voltage pulse between said first and second conductive silicide layers to form a filament between said first and second conductive layers, said filament extending from said second conductive layer down said sidewall of said emitter structure and under said spacer ring to said second conductive layer.
In another aspect the invention provides an antifuse comprising:
(a) a silicided single polysilicon bipolar transistor structure comprising:
(i) a collector layer,
(ii) a base layer overlying said collector layer and having an upper surface,
(iii) an emitter structure overlying said base layer, said emitter structure projecting above said base layer and having a sidewall extending above said base layer, said emitter structure also having an upper surface,
(iv) an oxide spacer ring surrounding said sidewall of said emitter structure, said spacer ring being formed by chemical vapor deposition and anisotropic plasma etching and being of narrow and well defined thickness,
(v) a first conductive silicide layer on said upper surface of said base layer, surrounding said spacer ring, and a second conductive silicide layer on said upper surface of said emitter structure, said first and second conductive silicide layers not contacting each other,
(b) and a conductive filament extending between said first and second conductive layers, said filament extending from said first conductive layer down said sidewall of said emitter structure and under said spacer ring to said second conductive layer.
In a third aspect the invention provides a method of making an antifuse in a silicided double polysilicon bipolar transistor, said transistor comprising:
(i) a collector, emitter and base, said collector being located beside said emitter and said emitter being located beside said base, each of said collector, emitter and base having a lower portion,
(ii) the lower portion of said emitter having a sidewall,
(iii) the lower portion of said emitter including a first polysilicon layer and a first conductive silicide layer, and the lower portion of said base including a second polysilicon layer and a second conductive silicided layer, said first and second conductive silicided layers not contacting each other, said method comprising providing a narrow oxide spacer ring surrounding said sidewall of said lower portion of said emitter, said spacer ring being formed by chemical vapor deposition and anisotropic plasma etching, said method further comprising applying a voltage pulse between said first and second conductive silicide layers to form a filament between said first and second conductive layers, said filament extending under said spacer ring.
In a fourth aspect the invention provides an antifuse comprising:
(a) a double silicided polysilicon bipolar transistor structure comprising a collector, emitter and base, said collector being located beside said emitter and said emitter being located beside said base, each of said collector, emitter and base having a lower portion,
(b) the lower portion of said emitter having a sidewall,
(c) the lower portion of said emitter including a first polysilicon layer and a first conductive silicide layer, and the lower portion of said base including a second polysilicon layer and a second conductive silicide layer, said first and second conductive silicided layers not being in contact with each other,
(d) said emitter having an oxide spacer ring surrounding said sidewall of said lower portion of said emitter, said spacer ring being formed by chemical vapor deposition and anisotropic plasma etching and being of narrow and well defined thickness,
(e) and a conductive filament extending from said first conductive silicide layer under said spacer ring to said second conductive silicided layer.
Further objects and advantages of the invention will appear from the following description, taken together with accompanying drawings.
REFERENCES:
patent: 3742592 (1973-07-01), Rizzi et al.
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patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4796075 (1989-01-01), Whitten
patent: 5019878 (1991-05-01), Yang et al.
patent: 5208177 (1993-05-01), Lee
patent: 5298784 (1994-03-01), Gambino et al.
patent: 5316971 (1994-05-01), Chiang et al.
patent: 5565702 (1996-10-01), Tamura et al.
patent: 2222024 (1990-02-01), None
patent: WO 8503599 (1985-08-01), None
David J. Roulston, Bipolar Semiconductor Devices, McGraw-Hill, (1990) pp. 340-347.*
Shacham-Diamand Y.: Filament Formation And The Final Resistance Modeling In Amorphous-Silicon Vertical Programmable Element, IEEE Transactions on Electron Devices, vol. 40, No. 10, Oct 1, 1993, pp. 1780-1788, XP000403559.
Appelman Petrus T.
Cervin-Lawry Andrew V. C.
Kendall James D.
Roubakha Efim
Bereskin & Parr
Carroll J.
Gennum Corporation
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