Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-05-05
2001-04-24
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C148S033500, C257S435000, C257S436000, C257S437000, C438S719000, C438S723000, C438S724000, C438S740000
Reexamination Certificate
active
06221776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to a method and system in which a sacrificial anti-reflective coating is used to protect an underlying, lower elevation silicon-based material from being etched while removing an underlying higher elevation silicon-based material.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been formed within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed across the semiconductor topography and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact areas are placed through the dielectric to electrically link the interconnect routing to select impurity regions extending across the substrate. A second level of interconnect routing may be placed across a second level of interlevel dielectric arranged above the first level of interconnect routing. The first and second levels of interconnect routing may be coupled together by contact structures arranged through the second level of interlevel dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed, if desired.
Patterning the various structures of an integrated circuit involves selectively removing portions of one material while other materials are maintained intact. Wet etch techniques typically demonstrate a high selectively for one material relative to other materials. Wet etch techniques, however, are generally isotropic. That is, wet etching occurs at the same rate in all directions. Therefore, if the thickness of a material being etched is comparable to the minimum pattern dimension, isotropic etching can cause undercutting into the critical dimension. Thus, the size and shape of an etched feature defined using an isotropic etch may be altered from their design specifications. For example, the slope of the sidewalls of the etched feature is often not formed to the desired specific angle. In order to preserve profile integrity, wet etching has given way to a “dry”, anisotropic etch technique which occurs at a faster rate in a vertical direction than in a horizontal direction.
Dry etching offers an important manufacturing advantage of eliminating the handling, consumption, and disposal of relatively large quantities of dangerous acids and solvents typically used to wet etch various thin films. More importantly, dry etching is better suited for maintaining the critical profile of a structure, particularly as minimum pattern dimensions continue to shrink. One drawback of the dry etch technique, however, is that it may be difficult to achieve a high selectivity of one silicon-based material relative to other silicon-based materials. For example, a high etch selectivity of silicon nitride (Si
3
N
4
) relative to both silicon dioxide (SiO
2
) and silicon is particularly difficult to accomplish using a dry etch process. Unfortunately, it may be necessary to etch select portions of a silicon nitride (“nitride”) layer from a doped polycrystalline silicon (“polysilicon”) layer arranged above a silicon-based substrate in which field isolation regions comprising silicon dioxide (“oxide”) are formed. The polysilicon layer may be patterned to form various structures, e.g., a gate conductor of a MOS transistor employed by, e.g., an SRAM memory cell. The nitride layer may be formed across the polysilicon layer to electrically isolate particular polysilicon structures from conductive structures, e.g., contacts, which may be subsequently formed adjacent to those polysilicon structures.
It may be necessary to remove the nitride layer from certain polysilicon structures to permit contacts to be purposefully formed in electrical communication with those polysilicon structures. Unfortunately, because of the time demand and cost required to develop a dry etch chemistry and machine for achieving a high selectivity of nitride with respect to silicon and oxide, no adequate dry etch process has been currently developed. Absent a dry etch technique which exhibits a high selectivity of nitride to both silicon and oxide, the silicon-based substrate and the field oxide might be unintentionally etched while anisotropically etching the nitride layer. Consequently, dangling bonds and an irregular grain structure may result in the upper surfaces of the silicon-based substrate and the field oxide. It is believed that an irregular grain structure provides migration avenues through which foreign species can pass into active areas of the substrate and into the field isolation regions. Further, the dangling bonds may promote the trapping of those foreign species in the active areas and the field isolation regions. The presence of those foreign species might lead to various problems, such as increased current leakage between active areas.
It would therefore be of benefit to develop a method for exclusively etching one material without undesirably etching other materials using a dry etch process. Otherwise, the integrated circuit structures which employ those materials might suffer damage as a result of being etched. Although developing a new dry etch chemistry which is highly selective to a particular material relative to other materials would be useful, doing so would be too costly and time consuming. Therefore, it would be more desirable to form a barrier between the etch chemistry and those materials which do not require removal. Such a barrier would prevent the materials from being exposed to the etch gases, allowing the materials to remain intact during the etching of another material.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof in which a acrificial anti-reflective coating is used to protect a material from being etched. An “anti-reflective coating” is a polymer film which is highly absorbing and non-bleaching at the wavelength of light used to expose photoresist during optical lithography. The anti-reflective coating is “sacrificial” in that it is temporarily placed upon a semiconductor topography to serve its purpose and then entirely removed. Most of the materials employed by an integrated circuit may be selectively etched without significantly etching the anti-reflective coating. As such, a relatively thick portion of the anti-reflective coating may be placed across a substrate to inhibit the substrate from being etched while removing a first material beneath a relatively thin portion of the anti-reflective coating. The anti-reflective coating provides an etch stop barrier between the etch chemistry and the substrate. The presence of the anti-reflective coating thus serves to prevent the etchants from contacting and attacking the substrate. Therefore, the etch selectivity ratio of the silicon-based substrate relative to the silicon-based first material need not be relatively high to prevent significant etching of the substrate.
Broadly speaking, one embodiment hereof suggests forming an anti-reflective coating across a substrate and selectively etching a first layer of material arranged above a portion of the substrate at a substantially faster rate than the anti-reflective coating. The substrate may include various structures composed of the same material as the first layer of material as well as materials which are dissimilar from the first layer of material, yet are silicon-based. The etch stop layer is sufficiently thick to inhibit etching of the substrate materials. The substrate may include only one level of an integrated circuit, or it may include multiple levels of an integrated circuit. The first layer of material preferably belongs to structures which are spaced laterally apart and above the substrate.
The anti-reflective coating has a relatively high viscosity which allows it to “pool” in recess regions as it is spin-on deposited across a surface having elevational disparities. This f
Conley Rose & Tayon
Cypress Semiconductor Corp.
Daffer Kevin L.
Powell William
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