Anti-lock CPU clock control method, circuit and apparatus

Details Anti-lock CPU clock control method, circuit and apparatus Anti-lock CPU clock control method, circuit and apparatus

1996-05-01

1998-08-04

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327147, 327295, 327544, H03B 1900

Patent

active

057899525

ABSTRACT:
The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.

REFERENCES:
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5254888 (1993-10-01), Lee et al.
patent: 5378935 (1995-01-01), Korhonen et al.
patent: 5442774 (1995-08-01), Pickup et al.
patent: 5451892 (1995-09-01), Bailey
patent: 5625311 (1997-04-01), Nakatsu

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