Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-11-17
2003-02-18
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C327S382000, C326S083000
Reexamination Certificate
active
06522512
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an anti-latch-up circuit, particularly to an anti-latch-up circuit in a separate-source connection.
FIG. 1
represents a schematic illustration of a conventional anti-latch-up circuit in a separate-source connection. Here, the separate-source connection refers to a circuit configuration such that an electronic circuit is powered by a voltage source separate from the power source of the main circuit to which the electronic circuit belongs.
In the figure, diode
7
and voltage source
3
make up the anti-latch-up circuit and voltage source
3
is a separate source. Other circuit elements are constituents of the main circuit, where p-MOS transistor
4
and n-MOS transistor
5
constitute a CMOS inverter that serves as an output buffer. The output buffer (
4
,
5
) is powered by a voltage source for the transmission device
2
with the source of p-MOS transistor
4
connected to voltage source
2
and the source of n-MOS transistor being grounded. The output buffer (
4
,
5
) supplies an output signal from output point
6
of the CMOS output buffer (the junction between the drains of p-MOS transistor
4
and n-MOS transistor
5
). Hereinafter, voltage source
2
will be referred to as a transmission-side voltage source and voltage source
3
as an anti-latch-up voltage source.
Output buffer (
4
,
5
) supplies an output signal to a reception device
9
which is symbolically represented as input buffer
9
in FIG.
1
.
The anti-latch-up circuit made up of diode
7
and anti-latch-up voltage source
3
is arranged at an input section
8
of reception device
9
to protect it from a high-voltage noise.
The voltage of anti-latch-up voltage source
3
is set up to be higher than that of transmission-side voltage source
2
. Since the output signal of the CMOS inverter has a voltage level lower than or equal to that of transmission-side voltage source
2
, diode
7
is always reverse-biased insofar as the circuit operates normally.
When, however, the input section
8
of the reception device
9
incidentally picks up a noise of a voltage level higher than that of anti-latch-up source
3
, diode
7
is forward-biased. The current caused by the noise finds its way through forward-biased diode
7
to anti-latch-up source
3
to protect reception device
9
against the flow of the noise-induced current.
Should the anti-latch-up circuit made up of diode
7
and anti-latch-up source
3
not be provided and consequently the noise of a high voltage-level be received directly by reception device
9
, the noise will be likely to cause creation of a high concentration carrier which is in turn injected into the substrate of reception device
9
, thereby causing a latch-up to be triggered.
Accordingly, the anti-latch-up circuit serves to avoid triggering of a latch-up by conducting the noise-induced current to bypass reception device
9
.
While the anti-latch-up circuit serves to protect reception device
9
against the latch-up due to a high-level noise as described above, a problem encountered in the conventional anti-latch-up circuit has been that a latch-up can be caused by diode
7
depending on the order in which the two voltage sources are turned on.
Suppose an initial state in which transmission-side voltage source
2
is turned on while anti-latch-up voltage source
3
is still on switch-off.
In many cases, the circuitry of anti-latch-up source
3
is configured so that the output of anti-latch-up voltage source
3
keeps the ground potential when the voltage source
3
is switched off.
Accordingly, diode
7
is forward-biased when output
6
of the output buffer (
4
,
5
) is accidentally at a high logic level.
The forward bias occasionally causes an over-current to conduct through diode
7
, possibly causing a high concentration carrier to be injected into the reception device
9
. The injected high-concentration carrier tends to trigger a latch-up.
For this reason, diode
7
possibly causes a latch-up due to the sequence of the turn-on of the two voltage sources.
In order to avoid this disadvantage, the anti-latch-up circuit described above has been omitted in many practical cases.
However, while the omission of the anti-latch-up circuit will obviate occurrence of latch-up due to the over-current of diode
7
, an alternative problem has been encountered that the omission of the anti-latch-up circuit unavoidably carries about vulnerableness to a latch-up due to an incoming high-level static noise, as described above.
It is an object of the present invention to provide an anti-latch-up circuit that is latch-up-resistant regardless of the order of switching-on of the two voltage sources.
SUMMARY OF THE INVENTION
The anti-latch-up circuit for protecting a signal-reception device from latch-up possibly triggered in the signal-reception device comprises a voltage source activated separately from a signal-transmission device, a diode, buffer means and an output-control circuit.
The diode is connected between the voltage source and the input conductor of the signal-reception device so as to become forward-biased when the overvoltage in excess of the voltage of the voltage source is applied to the input conductor.
The buffer means provides an output of a first logic level or a second logic level in response to turn-off or turn-on, respectively, of the voltage source.
The output control circuit checks the signal-transmission device to provide an output when the buffer means provides an output of the first logic level and permits the signal-transmission device to provide an output when the buffer means provides an output of the second logic level.
When the input conductor picks up a noise having a voltage level higher than that of the voltage source, the diode is forward-biased and a current caused by the noise flows to the voltage source without conducting into the signal-reception device.
In this way, the voltage source and the diode cooperate to prevent carrier injection into the signal-reception device, thereby preventing possible occurrence of latch-up in the signal-reception device.
When the signal-transmission device is turned on while the voltage source is turned off, the buffer means provides an output of the first logic level. This output of the buffer means causes the output control means to control the output buffer circuit to be blocked from transmission of a signal to the input conductor of the signal-reception device.
In this way, the buffer means and the output control means cooperate to block a signal transmission while the voltage source is turned off, thereby preventing triggering of latch-up caused by the signal transmission to the input conductor while turn-off of the voltage source.
The signal-transmission device can be provided with an output buffer circuit fed with an operating voltage from a power supply. In this case, the output control means is series-connected to the power-supply path from said power supply to the output buffer circuit to check or permit a power supply to the output buffer circuit.
Preferably, the output buffer circuit is a CMOS buffer circuit and the output control means is a p-MOS transistor with a source connected to the power supply, a drain connected to the upper source of the CMOS buffer circuit and a gate connected to the output of the buffer means. In this case, the first logic level is prescribed to be a high level and the second logic level is prescribed to be a low level.
The buffer means can be provided on the side of the signal-reception device.
Alternatively, buffer means can be provided on the side of the signal-transmission device.
The buffer means can be made up of buffer circuits of multiple stages.
The above and other objects, features and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.
REFERENCES:
patent: 5546020 (1996-08-01), Lee et al.
patent: 5771140 (1998-06-01), Kim
patent: 5905621 (1999-
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