Anti-jitter circuits

Details Anti-jitter circuits Anti-jitter circuits

2001-08-01

2004-09-14

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S165000, C327S551000, C326S026000

Reexamination Certificate

active

06791393

ABSTRACT:

BACKGROUND OF THE INVENTION
An AJC is described in our European patent application No. 97903456.8 based on International patent application, publication No. WO 97/305 16. The described AJC circuit provides a unique way of reducing phase noise or time jitter on a frequency source, typically 20 dB or more for the or each (fully cascaded) stage. FIGS.
1
(
a
) to
1
(
c
) of the accompanying drawings illustrate the principle of operation of this earlier AJC. FIG.
1
(
a
) is a block circuit diagram of the system described in the earlier patent application, FIG.
1
(
b
) shows an input pulse train with jitter (shown in broken outline) on the central pulse and FIG.
1
(
c
) shows the corresponding integrator output (Op
2
) and the comparator switching level (Op
3
).
The present invention provides an improvement over this earlier AJC. Because the implementation of the core part of the improved AJC requires no d.c. power the term adiabatic anti-jitter circuit (AAJC) will be used hereinafter.
SUMMARY OF THE INVENTION
According to the invention there is provided an anti-jitter circuit for reducing time jitter in an input pulse train comprising:
an integrator charge storage means,
charging means for deriving from the input pulse train at least one charge packet during each cycle of the input pulse train and for supplying the charge packets to the integrator charge storage means, and
discharging means for continuously discharging the integrator charge storage means,
the charging means and the discharging means being operative to create on the integrator charge storage means a time varying voltage waveform having a mean d.c. voltage level, and
means for comparing said time varying voltage waveform with said mean d.c. voltage level and deriving an output pulse train as a result of the comparison.


REFERENCES:
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patent: 3883756 (1975-05-01), Dragon
patent: 4071781 (1978-01-01), Kayalioglu
patent: 4142110 (1979-02-01), Weber
patent: 4226219 (1980-10-01), Olmstead
patent: 5438289 (1995-08-01), Kan et al.
patent: 0 383 271 (1990-08-01), None
patent: 0 592 048 (1994-04-01), None
patent: 0 681 364 (1995-11-01), None
patent: 57207419 (1982-12-01), None
patent: WO 97/30516 (1997-08-01), None
Kraus, “Fast DC-coupled trigger,”Elec. World and Wireless World, 96,1651, p. 7 (1990).
Weiss, Richard, Time and Standard Frequency Receiver For DCF 77 With Back-Up Operation.,Funkschau, edition 22 pgs. 964-968, 1976.

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