Antenna selector switch

Details Antenna selector switch Antenna selector switch

1998-05-08

2001-03-20

Chin, Stephen (Department: 2734)

Pulse or digital communications

Transceivers

C375S297000

Reexamination Certificate

active

06205171

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a PCMCIA RF module. More specifically, the present invention relates to a wireless LAN transmitter/receiver utilizing direct sequence spread spectrum (DSSS) technology.
BACKGROUND OF THE INVENTION
The wireless local area network (LAN) represents a major trend in digital communications technology. IEEE specification 802.11 defines a direct sequence spread spectrum (DSSS) standard for wireless digital communication systems. A type of PCMCIA module which conforms to this standard includes an RF module, which provides the transmit/receive function. The focus of the present invention is the design of such an RF module.
A known configuration for a wireless LAN transmit/receive RF module, utilizing quadrature phase shift keyed (QPSK) modulation, is shown in block diagram form in FIG.
1
.
In the receive mode, as selected by the ANT SW command, transmit/receive antenna
100
,
102
routes a received signal through a DR image filter FL
1
to a transmit/receive (TX/RX) switch
1040
, within the RF power amplifier and TX/RX switch block
104
. The received signal (a QPSK modulated carrier at 2.4 GHz) is then amplified by low noise amplifiers (LNA)
106
and
1080
, and filtered again by DR image filter FL
2
. In the RF/IF converter block
108
, the carrier signal is down converted by mixer
1081
and a first local oscillator signal (2.1 GHz) from VCO
118
. The down converted output is a 280 MHz IF QPSK signal, which is selectively filtered by channel filter FL
3
. The IF QPSK signal is then amplified to a constant power level by limiting amplifiers
1101
and
1102
, within the Quadrature demodulator/modulator block
110
.
A second local oscillator signal (560 MHz) is supplied from VCO
116
to the I/Q LO
1107
, where it is digitally divided into an in-phase (I) 280 MHz signal and a 90-degree phase-shifted (Q) 280 MHz signal. The in-phase signal is fed to “I” mixer
1103
, and the phase-shifted signal is fed to “Q” mixer
1105
. The demodulated I and Q outputs (RXI and RXQ) represent the received baseband signals, and are filtered through low pass filters
1104
and
1106
.
In the transmit mode, the process is essentially reversed. Baseband signals TXI and TXQ are filtered through low pass filters
1108
and
1109
, and are then quadrature modulated by mixers
1110
and
1111
, utilizing in-phase and phase-shifted 280 MHz signals from I/Q LO
1107
. The 280 MHz IF QPSK output signal is amplified by amplifier
1112
, filtered by channel filter FL
5
, and up converted by mixer
1083
to 2.4 GHz, in conjunction with the first LO signal (2.1 GHz) from VCO
118
and amplifier
1082
. The up converted signal is filtered by DR image filter FL
6
, amplified by driver amplifier
1084
, and filtered again by filter FL
7
. Finally, it is amplified by Power Amplifier
1041
and routed via switch
1040
and filter FL
1
to transmit/receive antenna
100
,
102
.
There are numerous areas of design considerations for the performance improvement of the above described circuit. Those design areas relevant to the inventive wireless LAN transmitter/receiver disclosed herein are discussed below.
(1) Power Amplifier Linearity and Stability
An important parameter in the design of a QPSK modulation system is the linearity of the system. A potential source of nonlinearity is the power amplifier (PA) stage, so it is important that the drive level of this stage be maintained within a linear region (typically at least 3 dB below the compression point of the PA).
Another important design consideration for the PA stage is the speed and stability of its on-off switching, since this can be a limiting factor in QPSK performance. Therefore, it is very desirable to provide the PA with a stable, high speed on-off switching control circuit.
A typical prior art Power Amplifier circuit is shown in FIG.
2
. GaAs MESFET's are widely used as power amplifiers in modern communication systems, due to their high efficiency and low distortion characteristics at high power levels. In most applications, two or more stages of power amplifier devices are cascaded to provide high power gain with low driving power. In the prior art circuit of
FIG. 2
, a 3-stage MESFET amplifier (D
1
, D
2
, D
3
) is shown, with three corresponding gate inputs connected to a resistor network (Rg
11
, Rg
12
, Rg
21
, Rg
22
, Rg
31
, Rg
32
, and variable resistor R_adj). This resistor network provides an appropriate bias voltage to each of the gate inputs (Vg
1
, Vg
2
, Vg
3
, respectively) from a negative voltage supply, such as −5 volts. The variable resistor R_adj is used to trim the bias drain current.
In most modern wireless communication systems, the RF output signal is transmitted in bursts. Therefore, the PA stage is turned on only when transmitting, and must be off when receiving. In order to achieve a high transmission rate, the PA stage must be capable of a very high on-off rate. In the circuit of
FIG. 2
, a P-channel MOSFET Q
1
is used as the on-off switching device for PA D
1
, D
2
, D
3
. When Vctrl activates Q
1
through resistor R
1
, Vdd is connected to the drains of PA D
1
, D
2
, D
3
, and the PA stage is turned on. Conversely, when Vctrl turns Q
1
off, the PA stage is disconnected from Vdd, and is thus turned off.
A significant disadvantage of this prior art circuit approach is that the on-off switching takes place in the high current side of the PA stage, that is, between the drains and Vdd. For high power, high speed applications, the MOSFET switching device (Q
1
) must accommodate high current switching and discharging. Such MOSFET devices can be very expensive. Therefore, the circuit architecture of
FIG. 2
is not optimal for high power, high speed switching applications.
(2) Antenna Select Switch Circuit
Another important design consideration relates to the port isolation of the antenna select switch circuit. In a typical prior art single pole, double throw RF switching arrangement, as shown in
FIG. 3
, a common RF in/out port at node C can be switched to either Antenna
1
or Antenna
2
, depending on the bias condition of diodes D
1
and D
2
. A switching control voltage (Ant Sel) provides a bias current through the Bias Circuit, which is in series with diode D
1
, quarter wavelength transmission line MLIN, and diode D
2
, to ground. When Ant Sel is high, diodes D
1
and D
2
are forward biased (turned on), so that they act as short circuits to the RF carrier frequency Fo. With diode D
2
shorted to ground, quarter wavelength transmission line MLIN reflects an open (high impedance) at node C, thus preventing an RF signal from passing to Antenna
2
. At the same time, shorted diode D
1
provides a direct path for an RF signal to Antenna
1
.
When Ant Sel is low, diodes D
1
and D
2
are reverse biased (turned off), so that they act as open circuits to the RF carrier frequency. In this case, open circuited diode D
1
isolates node C from Antenna
1
, while quarter wavelength transmission line MLIN provides a through path due to the open circuited diode D
2
. Thus, an RF signal at node C is connected to Antenna
2
through MLIN.
An important disadvantage of the prior art circuit of
FIG. 3
is that this circuit is susceptible to diode parasitic effects, which can significantly degrade the port isolation of the off branch. This degradation can occur because diodes D
1
and D
2
are not perfect switches, due to their capacitive and inductive characteristics, as depicted in
FIGS. 4A-4C
.
FIG. 4A
shows the equivalent circuit of a diode model,
FIG. 4B
represents the diode in its off mode, and
FIG. 4C
represents the diode in the on mode. Referring to
FIG. 4A
, the inductor Ls represents the parasitic series inductance in both the on and off modes. The capacitor Cj represents the junction capacitance of the diode, and capacitor Ct represents the parasitic capacitance between cathode and anode terminals. The resistor Ron/Roff represents the diode resistance, depending on the diode mode (on or off).
In the off mode, as shown in
FIG. 4B
, resistor Ron/Roff is an

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