Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2007-09-25
2010-11-30
Jackson, Stephen W (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
07843673
ABSTRACT:
An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circuit path with an antenna diode and at least one diode protection circuit coupled in series. The diode protection circuit reduces or prevents EOS current from flowing through the diode circuit path during an EOS event.
REFERENCES:
patent: 6389584 (2002-05-01), Kitahara
patent: 6594809 (2003-07-01), Wang et al.
patent: 6934136 (2005-08-01), Duvvury
Ming-Dou Ker et al., ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique, SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip], Volume , Issue , Sep. 17-20, 2003 pp. 219-222.
Lai Weng Hong
Ng Kian Ann
Chartered Semiconductor Manufacturing Ltd.
Horizon IP Pte Ltd
Jackson Stephen W
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