Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Agitating or moving electrolyte during coating
Reexamination Certificate
2001-05-01
2004-02-24
Valentine, Donald R. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Agitating or moving electrolyte during coating
C205S157000, C205S640000, C204S264000, C204S266000, C204S276000, C204S292000, C118S610000, C118S612000
Reexamination Certificate
active
06695962
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an apparatus and a method to deposit, polish, or electro-polish metal films on a substrate, or to remove such metal films from such a substrate. The unique anode assembly is particularly suitable for providing planar metal deposits on damascene-type interconnect and packaging structures.
Multi-level integrated circuit manufacturing requires many steps of metal and insulator film depositions followed by photoresist patterning and etching or other means of material removal. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines or channels. Often, these features need to be filled with a specific material, such as a metal, a dielectric, or both. For high performance applications, the wafer topographic surface needs to be planarized, making it ready again for the next level of processing, which commonly involves deposition of a material, and a photolithographic step. It is most preferred that the substrate surface be flat before the photolithographic step so that proper focusing and level-to-level registration or alignment can be achieved. Therefore, after each deposition step that yields a non-planar surface on the wafer, there is often a step of surface planarization.
Electrodeposition is a widely accepted technique used in IC manufacturing for the deposition of a highly conductive material such as copper (Cu) into the features such as vias and channels opened in an insulating layer on the semiconductor wafer surface.
Electrodeposition is commonly carried out cathodically in a specially formulated electrolyte solution containing copper ions as well as additives that control the texture, morphology and plating behavior of the copper layer. A proper electrical contact is made to the seed layer on the wafer surface, typically along the circumference of the round wafer. A consumable Cu or inert anode plate is placed in the electrolyte solution. Deposition of Cu on the wafer surface can then be initiated when a cathodic potential is applied to the wafer surface with respect to an anode, i.e., when a negative voltage is applied to the wafer surface with respect to an anode plate.
The importance of overcoming the various deficiencies of the conventional electrodeposition techniques is evidenced by technological developments directed to the deposition of planar copper layers. For example, U.S. Pat. No. 6,176,992 to Talieh, entitled METHOD AND APPARATUS FOR ELECTROCHEMICAL MECHANICAL DEPOSITION, commonly owned by the assignee of the present invention, describes in one aspect an electro chemical mechanical deposition technique (ECMD) that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits.
U.S. application Ser. No. 09/740,701 entitled PLATING METHOD AND APPARATUS THAT CREATES A DIFFERENTIAL BETWEEN ADDITIVE DISPOSED ON A TOP SURFACE AND A CAVITY SURFACE OF A WORKPIECE USING AN EXTERNAL INFLUENCE, now U.S. Pat. No. 6,534,116, also assigned to the same assignee as the present invention, describes in one aspect a method and apparatus for plating a conductive material onto the substrate by creating an external influence, such as causing relative movement between a workpiece and a mask, to cause a differential in additives to exist for a period of time between a top surface and a cavity surface of a workpiece. While the differential is maintained, power is applied between an anode and the substrate to cause greater relative plating of the cavity surface than the top surface.
U.S. application Ser. No. 09/735,546 entitled METHOD AND APPARATUS FOR MAKING ELECTRICAL CONTACT TO WAFER SURFACE FOR FULL-FACE ELECTROPLATING OR ELECTROPOLISHING, filed on Dec. 14, 2000, now U.S. Pat. No. 6,482,307, describes in one aspect a technique for providing full face electroplating or electropolishing. U.S. application Ser. No. 09/760,757, entitled METHOD AND APPARATUS FOR ELECTRODEPOSITION OF UNIFORM FILM WITH MINIMAL EDGE EXCLUSION ON SUBSTRATE, filed on Jan. 17, 2001, now U.S. Pat. No. 6,610,190, describes in one aspect a technique for forming a flat conductive layer on a semiconductor wafer surface without losing space on the surface for electrical contacts.
In such above-mentioned processes, a pad or a mask can be used during at least a portion of the electrodeposition process when there is physical contact between the workpiece surface and the pad or the mask. The physical contact or the external influence affects the growth of the metal by reducing the growth rate on the top surface while effectively increasing the growth rate within the features.
In a metal deposition process using a soluble anode, it is necessary to minimize contamination of the deposited metal with anode sludge or anode fines. Typically, an anode bag is wrapped around the soluble anode to minimize this sort of contamination. In a conventional manner of copper electrodeposition for interconnect or packaging applications, as shown in
FIG. 1
, an anode bag or filter
150
is wrapped around an anode
152
. A suitable space separates the anode
152
from the cathode
154
in the deposition cell
156
. Agitation, recirculation or even filtration of the electrolyte solution
160
may be provided. During routine plating operations, anode sludge builds up in the anode sludge cavity
158
formed by the space between the anode
152
and the bag
150
. In the case of Cu plating, excessive anode sludge build-up affects the quality of the deposited metal on the cathode
154
in an adverse manner. In particular, the uniformity of the deposited metal becomes poorer because of changes in the electric field distribution. In addition, the plating voltage increases because of anode polarization. The copper ions are unable to diffuse fast enough through the sludge layer to meet the requirements of the cathode. Moreover, the resulting loss in plating efficiency may cause hydrogen to be plated or evolve at the cathode. For routine maintenance, the anode
152
is removed from the deposition cell
156
and cleaned or desludged before replacement.
A general depiction of a plating and planarization apparatus in which improved anode assemblies such as those of the present invention can be used is shown in FIG.
2
. The carrier head
10
holds a round semiconductor wafer
16
and, at the same time, provides an electrical lead
7
connected to the conductive lower surface of the wafer. The head can be rotated about a first axis
10
b
. The head can also be moved in the x and y directions represented in FIG.
2
. An arrangement which provides movement in the z direction may also be provided for the head.
Certain embodiments of a carrier head that may be used to hold the wafer
16
form the subject matter of co-pending U.S. patent application Ser. No. 09/472,523, titled WORK PIECE CARRIER HEAD FOR PLATING AND POLISHING, filed Dec. 27, 1999, now U.S. Pat. No. 6,612,915, the disclosure of which is incorporated herein by reference as non-essential subject matter. Certain embodiments of anode assemblies with anode bags which are useable in conjunction with such a carrier head form the subject matter of co-pending U.S. patent application Ser. No. 09/568,584, filed May 11, 2000, titled ANODE ASSEMBLY FOR PLATING AND PLANARIZING A CONDUCTIVE LAYER, now U.S. Pat. No. 6,478,936, the disclosure of which is also incorporated herein by reference as non-essential subject matter.
A pad
8
is provided on top of a round anode assembly
9
across from the wafer surface. The pad
8
may have designs or structures such as those forming the subject matter of co-pending U.S. patent application Ser. No. 09/511,278, titled PAD DESIGNS AND STRUCTURES FOR A VERSATILE MATERIALS PROCESSING APPARATUS, filed Feb. 23, 2000, now U.S. Pat. No. 6,413,388. The disclosure of this co-pending application is also incorporated by reference herein as non-essential su
Basol Bulent M.
Talieh Homayoun
Uzoh Cyprian E.
Crowell & Moring LLP
NuTool Inc.
Valentine Donald R.
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