Telephonic communications – Audio message storage – retrieval – or synthesis – Digital signal processing
Reexamination Certificate
2000-12-12
2003-03-11
Tieu, Binh (Department: 2643)
Telephonic communications
Audio message storage, retrieval, or synthesis
Digital signal processing
C379S032010, C379S088160, C379S088270, C704S258000
Reexamination Certificate
active
06532278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an announcement device in a switching system, and more particularly to an announcement device including a virtual recorder in an electronic switching system.
2. Background of the Related Art
In general, an announcement device is a device for providing announcement services, i.e., recording the contents of voice services provided by a telecommunication service provider, and playing, or announcing the recorded voice data for the subscriber.
Referring to
FIG. 1
, a related art announcement device
10
includes a switch matching, control section
11
to control announcement functions and record/monitor announcement functions, and a main switch block
20
to send and receive information to/from the announcement device
10
. A switch sub-highway (SHW) channel
15
is provided for inputting/outputting frame synchronization signals FS, clock signals CLK, and voice data (Rx Data/Tx Data) to/from the announcement device
10
and the switch
20
, in accordance with control signals of the SHW section
11
.
FIG. 2
shows input/output structures of voice memory signals within the switch sub-highway section
11
in FIG.
1
. Specifically, the signals include an address signal, a data signal, a chip select (CS), a write enable (WE), and an output enable (OE).
FIG. 3
illustrates a series of voice signals, which have been inputted to the SHW section
11
of the announcement device
10
. The voice signals are received as serial data, and inputted to a voice memory
11
b
in the form of parallel voice signals through the series-parallel converting section
11
a.
The parallel data is then converted to series data by a parallel-series (PS) connecting section
11
c.
The voice data is then outputted to a switch block
20
through the SHW channel
15
.
Additional detail on the series-parallel converting section
11
a
is shown in
FIG. 4
, and additional detail of the parallel-series converting section
11
c
is shown in FIG.
5
. With respect to
FIG. 4
, the series-parallel converter
11
a
receives the serial voice data signals, along with a clock signal and a clear signal. In response, the series-parallel converter
11
a
generates parallel voice data. Next, referring to
FIG. 5
, the parallel-series converter
11
c
receives parallel voice signals from the voice memory
11
b,
along with a clock signal and a SH/LO signal, and outputs serial voice data.
An operation of the related art announcement device constructed above will now be described.
The SHW channel
15
typically consists of 64 voice channels. While the number of channels may be variable in each announcement device, an operation with 64 voice channels will be exemplified herein below.
As shown in
FIG. 1
, the SHW channel
15
comprises a FS, which is a reference clock signal signifying a start of channel “
0
”, and a clock signal CLK providing a time clock for the transmission of voice data, such as Rx Data and Tx data. The FS signal is operated at 8 KHz, while the clock signal CLK is operated at 8 MHz. Therefore, a total of 1,024 clock signal CLK periods exist in a single FS signal period.
The SHW control section
11
controls the FS signals, CLK signals, Rx Data, and Tx Data in the SHW channel
15
. Under normal conditions, that is, when the system is not recording, all of the 64 channels are used for announcement services. If, in the normal condition, a request for an announcement is received from a high level processor, the SHW control section
11
loads an announcement message stored in the voice memory on a particular SHW channel among the 64 voice channels of the SHW channel
15
.
Here, 16 clock signals CLK comprise one channel or a time slot, and 64 channels exist in a single FS signal. Since the SHW channel
15
is in serial lines, the FS signals and the CLK signals constitute each line to consecutively operate to conform to the FS signals. In other words, as shown in
FIG. 6
, if voice data synchronized as 16 CLK signals in accordance with the FS signals are outputted to each channel, 64 announcement services can be performed through 64 channels in the 1,024 clock signals.
If an address of a particular channel is latched by the SHW control section
11
in accordance with the FS signals and the CLK signals, the voice memory storing the voice messages outputs voice data in accordance with the address. The outputted parallel voice data is converted to series voice data so as to be outputted as Tx Data through a prescribed channel of the SHW channel
15
.
Recorded voice data is stored in the voice memory
11
b,
which is constructed in parallel FIG.
2
). In other words, data in the voice memory
11
b
comprises 20 address signals (address
0
-
20
), 8 data signals (data
0
-
7
), and control signals chip select (CS), write enable (WE), and output enable (OE).
In general, voice is considered to be a single series of analog signals. An analog voice signal is converted to a digital voice signal by an analog-digital converting circuit (CODEC, not illustrated in the drawings) in a voice terminal. In order to store such digitally converted series of voice data in the voice memory
11
b,
a parallel conversion is required. To do this, the series-parallel (S/P) converting section
11
a
converts the serial voice data to parallel voice data for storage in the voice memory
11
b.
By contrast, in order to provide a desired announcement service with the voice data stored in the voice memory
11
b,
the voice data must be transferred to a switch block
20
via the SHW
15
. Since the SHW
15
is configured for serial signals, the stored parallel signal data must first be converted to serial data through the parallel-series converting section
11
c
(FIG.
3
).
The voice data loaded on each channel occupies a prescribed channel of the SHW channel
15
, and is outputted to a main switch block
20
. An announcement service is thereby provided.
FS signals and clock signals CLK are also required for recording or reproducing announcements by the announcement device using serial voice data inputted/outputted to and from a voice terminal. The FS signals and clock signals CLK of the SHW channel
15
for voice services are used for that purpose.
Referring to
FIG. 7
, once a recording starts, an address latch signal for selecting a particular address signal of the voice memory
11
b
is synchronized with the clock signals CLK of the channel
0
memory location. A real address of the voice memory is selected in accordance with the address latch signal. The recorded serial voice data is latched in accordance with each clock signal CLK, and is converted to parallel data. Voice data is outputted in accordance with the data latch signals, thereby storing the voice data in a prescribed address of the voice memory
11
b
in accordance with the latched address signals. Specifically, the parallel data inputted/outputted to and from the voice memory comprises 8 bit data, consisting of bits D
0
-D
7
.
If a series of voice signals are inputted, the series-parallel circuit operates in conformity with a clock signal CLK.
Next, the clock signal CLK is a dually divided signal of the original clock signal to convert 8 MHz to 4 MHz. One channel includes 8 clock signals CLK. In other words, while one channel includes 16 clock signals CLK in the original 8 MHZ, another channel includes 8 clock signals CLK in the divided 4 MHz. Accordingly, D
7
is outputted from the first CLK, D
6
is outputted from the second CLK, and D
0
is outputted from the eighth CLK. The data outputted in conformity with the clock signal CLK are latched and stored in the circuit. Therefore, the data is continuously updated in conformity with the clock signal CLK, and necessary data can be latched and taken at the point of time when D
7
-D
0
are outputted.
The recorded voice can then be played back for monitoring in the same manner as recording. That is, when an address signal is outputted by the address latch signal from the channel
0
memory location in accordance with the FS signals and CLK signals, t
Fleshner & Kim LLP
LG Electronics Inc.
Tieu Binh
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