Annealing of a crystalline perovskite ferroelectric cell

Details Annealing of a crystalline perovskite ferroelectric cell Annealing of a crystalline perovskite ferroelectric cell

1998-11-20

2001-08-14

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000, C438S253000, C438S396000, C438S381000, C257S295000, C257S306000, C257S310000

Reexamination Certificate

active

06274388

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to ferroelectric structures integrated onto substrates such as silicon. In particular, the invention relates to the fabrication process of producing a crystallographically oriented ferroelectric structure.
BACKGROUND ART
Considerable interest exists in fabricating integrated circuit (IC) memories which are non-volatile, that is, ones that continue to store data after the IC chip has been powered down. One type that is reaching the market is a ferroelectric memory in which the gap between the capacitors of an electrode is filled with a ferroelectric material which can be electrically poled into two stable states. The commercial activity to date has involved polycrystalline ferroelectric materials. Despite intensive developmental efforts, these polycrystalline ferroelectric IC memories exhibit poor fatigue characteristics and suffer from low yield in manufacture.
In an alternative approach under development, the ferroelectric material is grown in a crystallographically oriented phase. It is believed that under the proper conditions the ferroelectric grows in a columnar multicrystalline structure with the <001> axis of the layered perovskite crystal structure of typical ferroelectrics being preferentially oriented normal to the ferroelectnc film. Examples of the ferroelectric materials include lead zirconium titanate (PZT), lead lanthanum zirconium titanate (PLZT), lead niobium zirconium titanate (PNZT). Columnar crystallites are formed with random orientation within the plane of the film.
Dhote and Ramesh, two of the present inventors, have disclosed two distinct but related structures in U.S. patent applications, Ser. No. 08/578,499 filed Dec. 26, 1995 now issued as U.S. Pat. No. 5,798,903, and Ser. No. 08/582,545 filed Jan. 3, 1996 now issued as U.S. Pat. No. 5,777,356, both incorporated herein by reference in their entireties. The structure of the latter patent application is illustrated in the cross-sectional view of FIG.
1
. An illustrated ferroelectric random access memory (FRAM) cell
20
, of which many are formed in the IC memory, is formed on a <001>-oriented crystalline silicon substrate
22
and includes both a ferroelectric capacitor and a transistor. A metal-oxide-semiconductor (MOS) transistor is created by forming source and drain wells
24
,
26
having a conductivity type opposite to that of the substrate
22
. The intervening gate region is overlaid with a gate structure
28
including a lower gate oxide and an upper metal gate line, for example of aluminum, to control the gate.
A first inter-level dielectric layer
30
is deposited over the substrate and the transistor structure. A through hole
32
is etched through the first inter-level dielectric layer
30
in the area over the source well
24
, and polysilicon is filled into the through hole
32
to form a polysilicon contact plug to the transistor source. A metal source line
34
is photolithographically delineated on top of the first inter-level dielectric layer
30
and electrically contacts the polysilicon plug.
A second inter-level dielectric layer
36
is then deposited over the first inter-level dielectric layer
30
. Another through hole
38
is etched through both the first and second interlevel dielectric layers
30
,
36
over the area of the drain well
26
, and polysilicon is filled into the second through hole
38
to form a contact plug to the transistor drain.
A lower ferroelectric stack is then deposited and defined. It includes a polysilicon layer
40
to promote electrical contact to the polysilicon plug
38
, a titanium nitride (TiN) layer
42
acting as a first conductive barrier between the underlying polysilicon and the oxidizing ferroelectric layer and its oxide electrodes, an intermetallic layer
44
acting as the primary barrier, and a lower metal-oxide electrode
46
.
Growth of the metal-oxide electrodes
46
,
52
and the ferroelectric layer
50
is performed at temperatures in the range of 500° to 650° C., the highest temperatures achieved in the processing after the deposition of the intermetallic layer
44
.
The intermetallic layer
44
is novel to the second cited patent. It may have a composition of Ti
3
Al, among other possibilities to be discussed later. In brief, an intermetallic is an alloy of at least two metals, one of which is refractory, and the metals are combined in stoichiometric or near stoichiometric ratios. There results a metal with long-range atomic order, that is, a metal that is at least polycrystalline. Liu et al. provide a good introduction to intermetallics, at least as used for mechanical components, in “Ordered Intermetallics,”
ASM Handbook
, vol. 2
, Properties and Selection: Nonferrous Alloys and Special-Purpose Materials
(ASM International, 1992) pp. 913-942).
The lower metal-oxide electrode may have a composition of lanthanum strontium cobaltite (LSCO), which forms ia a perovskite crystal structure and in particular a composition of approximately La
1−x
Sr
x
CoO
3
, where 0.15
3
×
3
0.85. It is now well known that LSCO forms an acceptable electrical contact and further promotes highly oriented growth of perovskite ferroelectric materials. Several variations on the structure of the lower ferroelectric stack are possible. Neither the polysilicon layer
40
nor the TiN layer
42
is considered crucial, and either or both may be dispensed with.
A Z-shaped field-oxide layer
48
is formed around the sides of the lower ferroelectric stack and extends over its rim and laterally outwards from its bottom but leaves a central aperture for the after deposited upper ferroelectric stack.
The upper ferroelectric stack is then deposited and defined to fill the aperture of the field oxide layer
48
but not to extend beyond the end of its foot. The upper ferroelectric stack includes the ferroelectric layer
50
, for example of PNZT, the upper metal-oxide electrode layer
52
, for example of LSCO, and a platinum layer
54
.
A third inter-layer dielectric layer
56
is deposited around the upper and lower ferroelectric stacks. A via hole
60
is etched down to the platinum layer
54
, and Ti/W is filled into the hole to form a via
60
contacting the platinum layer
54
. An aluminum layer is deposited and delineated to form an interconnect line
62
connected to the via
60
.
Prototype ferroelectric capacitor stacks have been grown following the vertical stack structure shown in FIG.
1
. Both the LSCO electrodes
46
,
52
and the ferroelectric layer
50
have been shown to exhibit highly crystalline orientation. The ferroelectric stacks were measured to have polarization, fatigue, and retention properties superior to those available from polycrystalline ferroelectric cells.
Nonetheless, the results still need improvement. The cell manufactured according to the process exhibits a hysteresis curve adequate for operation at 5V. However, for high-level integration, 3V operation is greatly desired. The polarizability of the ferroelectric cell needs to be improved for 3V operation.
SUMMARY OF THE INVENTION
The invention can be summarized as a method of fabricating a perovskite layer over a metal-oxide layer. At least the metal-oxide layer is subjected to a rapid thermal anneal after its deposition.
A ferroelectric memory cell is formed over a silicon substrate with an intermediate intermetallic layer. A ferroelectric cell is formed by the sequential growth of a lower metaloxide electrode, a ferroelectric layer, and an upper metal-oxide layer. At least the lower metal-oxide electrode is annealed for a relatively short time at a temperature above the temperature at which it was grown.
In another aspect of the invention, the intermetallic layer is formed of a silicide, most preferably a disilicide of a refractory metal.
In yet another aspect of the invention, a second intermetallic layer is formed over the upper metal-oxide layer to provide electrical contacting to an upper metal level. The second intermetallic layer eliminates the need for platinum on the upper side. More preferably, the s

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