Annealing method for III-V deposition

Details Annealing method for III-V deposition Annealing method for III-V deposition

1987-11-13

1989-05-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG25, 148DIG48, 148DIG65, 148DIG94, 148DIG97, 148DIG110, 156613, 437126, 437132, 437247, 437936, 437939, 437963, 437973, H01L 2120, H01L 21324

Patent

active

048351164

ABSTRACT:
A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.

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