Angled nitrogen ion implantation for minimizing mechanical...

Details Angled nitrogen ion implantation for minimizing mechanical... Angled nitrogen ion implantation for minimizing mechanical...

1999-04-06

2001-09-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S425000, C438S426000, C438S440000, C438S433000, C438S434000, C438S443000, C438S444000, C438S445000, C438S447000

Reexamination Certificate

active

06284626

ABSTRACT:

TECHNICAL FIELD
This invention relates to technology for isolating active device regions in integrated circuits such as shallow trench isolation (STI) technology, and more particularly, to a method for fabricating an isolation trench having at least one side wall with nitrogen ions implanted therein to minimize mechanical stress on the at least one side wall of the isolation trench from the insulator material filling the isolation trench.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, for integrated circuits fabricated on a semiconductor wafer
102
, an epitaxial silicon layer
104
is deposited on the semiconductor wafer
102
. An active device region
106
is isolated within the epitaxial silicon layer
104
by a first isolation trench
108
and a second isolation trench
110
, as is common in shallow trench isolation (STI) technology. In the example of
FIG. 1
, the active device region
106
includes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain
112
, a source
114
, and a gate oxide
116
fabricated within the active device region
106
.
FIG. 2
, which includes
FIGS. 2A
,
2
B,
2
C,
2
D,
2
E, and
2
F, illustrates the fabrication of the first and second isolation trenches
108
and
110
. Elements having the same reference numeral in
FIGS. 1
,
2
A,
2
B,
2
C,
2
D,
2
E, and
2
F refer to elements having similar structure and function. Referring to
FIG. 2A
, after the epitaxial silicon layer
104
is deposited on the semiconductor wafer
102
, a pad oxide layer
202
comprised of silicon dioxide is deposited on the epitaxial silicon layer
104
. Then, a nitride layer
204
comprised of silicon nitride is deposited on the pad oxide layer
202
. The first isolation trench
108
and the second isolation trench
110
are patterned and etched using conventional photoresist patterning technology as known to one of ordinary skill in the art of integrated circuit fabrication.
The first isolation trench
108
and the second isolation trench
110
are etched in the epitaxial silicon layer
104
through the nitride layer
204
and the pad oxide layer
202
. The first isolation trench
108
and the second isolation trench
110
each have at least one side wall and a bottom wall. In the example of
FIG. 2A
, the at least one side wall and the bottom wall of the first and second isolation trenches
108
and
110
are formed by the semiconductor material (i.e. silicon in the example of
FIG. 2
) of the epitaxial silicon layer
104
.
Referring to
FIG. 2B
, once the first isolation trench
108
and the second isolation trench
110
are etched, a linear oxide layer
206
which is a layer of insulator material is thermally grown from the at least one side wall and the bottom wall of the first isolation trench
108
and the second isolation trench
110
, as known to one of ordinary skill in the art of integrated circuit fabrication. Such thermal growth ensures a structurally smooth transition from the silicon at the at least one side wall and the bottom wall of an isolation trench to the silicon dioxide filling the isolation trench.
Referring to
FIG. 2C
, once the linear oxide layer
206
is thermally grown from the at least one side wall and the bottom wall of the isolation trenches
108
and
110
, the isolation trenches
108
and
110
are filled with insulator material
208
such as silicon dioxide using a deposition process as known to one of ordinary skill in the art of integrated circuit fabrication. Typically, to enhance the insulating capability of the insulator material
208
such as the silicon dioxide filling the isolation trenches
108
and
110
, the insulator material
208
thus deposited is densified using a thermal densification process as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIG. 2D
, the insulator material
208
is then polished down to the nitride layer
204
using a chemical mechanical polishing (CMP) process, as known to one of ordinary skill in the art of integrated circuit fabrication. The nitride layer
204
acts as a stop layer in the chemical mechanical polishing (CMP) process. Referring to
FIG. 2E
, the nitride layer
204
is then removed, and the active device region
106
is defined by ion implantation for forming devices of the integrated circuit including the drain
112
and the source
114
of a MOSFET. The pad oxide layer
202
is a sacrificial oxide layer which minimizes damage to the surface of the epitaxial silicon layer
104
during this ion implantation. Referring to
FIG. 2F
, the pad oxide layer
202
is then etched (as well as the top portion of the insulator material
208
filling the isolation trenches
108
and
110
), and the gate oxide of the MOSFET within the active device region
106
is fabricated.
FIGS. 1
,
2
A,
2
B,
2
C,
2
D,
2
E, and
2
F illustrate ideal shapes for isolation trenches
108
and
110
. Referring to
FIG. 3
, a more realistic shape for the first isolation trench
108
within the box with the dashed lines in
FIG. 2C
is shown. The side wall
302
of the first isolation trench
108
is not perfectly vertical, but rather is sloped. In addition, as illustrated in
FIG. 3
, the top and bottom of the side wall
302
is rounded to form a bird's beak at the side wall
302
of the first isolation trench
108
, as known to one of ordinary skill in the art of integrated circuit fabrication. Such corner rounding occurs during thermal growth of the layer of insulator material
206
from the side wall and the bottom wall of the first isolation trench
108
as the semiconductor material at the side wall and the bottom wall of the first isolation trench
108
is consumed during such a process.
The amount of such corner rounding may be measured by the radius of a circle
304
that fits to the rounded comer at the top of the side wall
302
of the first isolation trench
108
, as shown in FIG.
3
. Referring to
FIGS. 2C and 3
, such corner rounding reduces the effective area of the active device region
106
. As device densities continuously increase and as device geometries continuously decrease with design of smaller geometry active device regions, such reduction in the effective area of the active device region
106
is especially disadvantageous.
In addition, the side wall
302
of the isolation trench
108
is subject to mechanical stress from the insulator material
208
filling the isolation trench
108
. Such mechanical stress may form especially from the thermal densification of the insulator material
208
filling the isolation trench
108
as the insulator material
208
expands or contracts within the isolation trench
108
. Referring to
FIGS. 2C and 3
, such mechanical stress has a detrimental effect on the devices within the active device region
106
adjacent the isolation trench
108
. As described in a technical journal article with title “Mechanical Stress Induced MOSFET Punch-Through and Process Optimization for Deep Submicron TEOS-O
3
filled STI Device,” by K. Ishimaru at al. in the Symposium on VLSI Technology Digest of Technical Papers, 1997, pages 123-124, such mechanical stress results in failure of devices within the active device region
106
. For the example of the MOSFET within the active device region
106
, the MOSFET has higher leakage current from such mechanical stress which may lead to failure of the integrated circuit.
Thus, a process for forming a filled isolation trench such as in shallow trench isolation (STI) technology which results in minimized corner rounding and/or in reduced mechanical stress on the side wall of the isolation trench is desired.
SUMMARY OF THE INVENTION
Accordingly, the present invention uses nitrogen ion implantation for fabrication of a filled isolation trench such as in shallow trench isolation (STI) technology with minimized corner rounding and reduced mechanical stress on the at least one side wall of the isolation trench.
Generally, the present invention is a method for fabricating a filled isolation trench as part of an integrated circuit on a semiconductor wafer,

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