AND-gate clock

Details AND-gate clock AND-gate clock

1979-08-13

1981-09-15

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 1908, H03K 1920

Patent

active

042899737

ABSTRACT:
An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates the input stage from the output stage when only one signal is true, therefore preventing power dissipation by current flow through the output driver stage. The isolation stage provides an alternative current path through smaller transistors, thereby incurring lesser power dissipation and requiring less layout area. A small driver stage may then be used.

REFERENCES:
patent: 3601624 (1971-08-01), Hayes
patent: 3644750 (1972-02-01), Campbell
patent: 3898479 (1975-08-01), Proebsting
patent: 3927334 (1975-12-01), Callahan
patent: 3943496 (1976-03-01), Padgett
patent: 4061933 (1977-12-01), Schroeder et al.

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