AND circuit and address circuit employing the same

Details AND circuit and address circuit employing the same AND circuit and address circuit employing the same

1991-07-31

1993-06-08

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307449, 307480, 365177, 36518905, 36518908, H03K 1716, H03K 19003

Patent

active

052182410

ABSTRACT:
An AND circuit having a first input terminal, a second input terminal and an output terminal, and is defined by a P-channel MOS FET, an N-channel MOS FET, a NPN bipolar transistor and a resistor. The P-channel MOS FET has a source connected to the first input terminal and a gate connected to the second input terminal. The N-channel MOS FET has a gate connected to the second input terminal, a source connected to the ground and a drain connected to the drain of the P-channel MOS FET. The transistor has a base connected to the drain of the P-channel MOS FET, and the collector-emitter thereof connected between an electric power supply line and the ground. The resistor is connected in series to the collector-emitter of the transistor. One end of the resistor is connected to the output terminal. The AND circuit has less MOS FETs so that the layout area can be reduced.

REFERENCES:
patent: 3050640 (1962-08-01), Dillingham et al.
patent: 3986042 (1976-10-01), Padgett et al.
patent: 4858188 (1989-08-01), Kobayashi

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